Auxiliary Conductor Layout for Faster Semiconductor Package Traces

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Solution Overview

Problem

As semiconductor packages operate at higher speeds, existing trace patterns face challenges in efficiently transmitting signals due to increased time delays, which are exacerbated by the arrangement of trace patterns, particularly with bending portions that cause signal delays.

Innovation Solution

Incorporating a first auxiliary conductor with end portions coupled to the trace pattern, which bypasses portions of the trace pattern, reducing inductance and increasing capacitance to lower impedance and time delay, thereby enhancing signal transmission speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If trace patterns are arranged to connect semiconductor die, then signal transmission path is established, but time delay increases and signal transmission speed decreases

Engineering Contradiction:
Improvesignal transmission speedVSAvoidtime delay
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The auxiliary conductor is divided into multiple segments (first auxiliary conductor segment, second auxiliary conductor segment, third auxiliary conductor segment) that are respectively coupled to different portions of the trace pattern. This segmentation allows the auxiliary conductor to provide multiple parallel signal transmission paths, reducing the overall time delay while maintaining connection between the semiconductor die and package substrate

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The auxiliary conductor acts as an intermediary element coupled between the trace pattern and reference voltage. By introducing this intermediate conductive structure, the patent creates additional capacitance and provides alternative signal transmission paths that reduce the inductance and time delay of the original trace pattern

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If auxiliary conductor is coupled to trace pattern, then inductance is reduced and capacitance is increased, but device complexity increases

Engineering Contradiction:
Improvesignal transmission qualityVSAvoidconductor structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The auxiliary conductor is strategically positioned and coupled only at specific locations along the trace pattern rather than uniformly throughout. The first, second, and third auxiliary conductor segments are coupled to different portions of the trace pattern, providing localized improvement in signal transmission quality without unnecessarily increasing overall device complexity

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The auxiliary conductor structure reduces time delay and impedance in signal transmission by providing a shortcut for high-speed signals, improving conductance and reducing resistance and inductance, thus addressing the limitations of traditional trace patterns.

Implementation Method 1

bypasses portions of the trace pattern, reducing inductance and increasing capacitance to lower impedance and time delay

Methodology Applied
Scientific EffectInductance reduction: Inductor

Implementation Method 2

bypasses portions of the trace pattern, reducing inductance and increasing capacitance to lower impedance and time delay

Methodology Applied
Scientific EffectCapacitance increase: Capacitance

Implementation Method 3

reducing inductance and increasing capacitance to lower impedance and time delay

Methodology Applied
Scientific EffectImpedance reduction: Electrical Impedance Tomography

Data Source

PatentUS20240379523A1Semiconductor packages including auxiliary conductor coupled to trace pattern
Publication Date: 2024.11.14 SK HYNIX INC
  • US20240379523A1 patent drawing
  • US20240379523A1 patent drawing
  • US20240379523A1 patent drawing

AI summary

A semiconductor package in which an auxiliary conductor is coupled to a trace pattern is presented. The semiconductor package includes a semiconductor die disposed over a package substrate including a trace pattern. The semiconductor package includes a first auxiliary conductor having a first end and a second end coupled to the trace pattern.