Auxiliary Electrode Partition Layout for Maskless OLED Deposition
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Solution Overview
Problem
Existing methods for depositing conductive coatings in opto-electronic devices, such as OLEDs, face challenges with high evaporation temperatures affecting mask reuse and pattern accuracy, and debris generation during removal processes, which increase costs and complexity, and are not suitable for all topographical features.
Innovation Solution
An opto-electronic device design featuring a nucleation-inhibiting coating (NIC) on one layer surface and a conductive coating on another, where the conductive coating is electrically coupled to a third electrode in a sheltered region, allowing selective deposition without the need for fine metal masks and reducing debris generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a fine metal mask is used during deposition of electrode material, then pattern accuracy is improved, but mask reuse ability deteriorates due to high evaporation temperatures
Solution Approach 1:
The patent removes the fine metal mask from the deposition process entirely. Instead of using a mask to define the electrode pattern, the invention uses selective deposition on regions with different topographical features (planar vs. non-planar surfaces), thereby eliminating mask-related issues with high evaporation temperatures and reuse limitations
Solution Approach 2:
The patent divides the deposition surface into distinct regions with different topographical characteristics (planar regions and non-planar regions such as recesses or protrusions). This segmentation allows selective deposition of conductive material on specific regions without requiring a mask, resolving the contradiction between pattern accuracy and mask durability
2Manufacturing precision
If laser drilling is used to remove unwanted electrode material, then pattern formation is improved, but manufacturing yield deteriorates due to debris generation
Solution Approach 1:
The patent performs preliminary action by creating non-planar topographical features on the substrate before deposition. This pre-structured surface enables selective condensation of conductive material during deposition, eliminating the need for subsequent laser drilling and associated debris generation that reduces manufacturing yield
Solution Approach 2:
The patent converts the potential harm of complex topographical features into a benefit by using the non-planar regions to guide selective deposition. The complex surface morphology, which might seem problematic, actually enables precise pattern formation without harmful removal processes, thereby improving both pattern formation and manufacturing yield
3Ease of manufacture
If conventional deposition methods are used, then manufacturing simplicity is maintained, but adaptability to various topographical features deteriorates
Solution Approach 1:
The patent applies local quality by creating regions with different topographical properties (planar vs. non-planar) on the substrate surface. These localized variations in surface morphology enable selective deposition in specific areas while maintaining overall manufacturing simplicity, thereby achieving both ease of manufacture and adaptability to various topographical features
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise and efficient deposition of conductive coatings, reducing manufacturing costs and complexity while accommodating various topographical features, thereby improving the yield and accuracy of opto-electronic device production.
Implementation Method 1
selective condensation or deposition of a conductive material in a pattern on a layer surface
Implementation Method 2
nucleation-inhibiting coating (NIC) disposed on a first layer surface
Data Source
AI summary
An opto-electronic device having a plurality of layers, comprising a nucleation-inhibiting coating (NIC) disposed on a first layer surface in a first portion of a lateral aspect thereof. In the first portion, the device comprises a first electrode, a second electrode and a semiconducting layer between them. The second electrode lies between the NIC and the semiconducting layer in the first portion. In the second portion, a conductive coating is disposed on a second layer surface. The first portion is substantially devoid of the conductive coating. The conductive coating is electrically coupled to the second electrode and to a third electrode in a sheltered region of a partition in the device.