Auxiliary Select Gate Line Driver for Variable Non-Volatile Memory Cells
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Solution Overview
Problem
Existing non-volatile memory technologies face inefficiencies in programming, erasing, and reading operations due to variations in memory cell characteristics, leading to potential program and erase failures.
Innovation Solution
Incorporation of an auxiliary select gate line driver that provides specific driving voltages to auxiliary select gate lines, allowing for enhanced programming, erasing, and reading efficiencies by operating in different modes based on memory cell characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-volatile memory performs programming operations, then data is stored in memory cells, but program failures occur due to variations in memory cell characteristics
Solution Approach 1:
The patent applies local quality by introducing an auxiliary select gate line that provides localized voltage control to specific memory cells. This allows different voltage conditions to be applied to different regions of the memory array, compensating for variations in memory cell characteristics and ensuring reliable programming across all cells despite manufacturing variations.
Solution Approach 2:
The patent changes the voltage parameter by introducing a selectable voltage level to the auxiliary select gate line. This voltage can be dynamically adjusted between different levels (e.g., 0V, Vpp, Vcc) depending on the programming requirements and memory cell state, enabling adaptive control over the programming process to overcome cell characteristic variations.
2Reliability
If conventional non-volatile memory performs erasing operations, then data is cleared from memory cells, but erase failures occur due to variations in memory cell characteristics
Solution Approach 1:
The auxiliary select gate line enables localized voltage control during erase operations, allowing different voltage conditions to be applied to different memory regions. This compensates for erase failures caused by memory cell characteristic variations by providing tailored voltage levels to specific cells that need additional erase support.
Solution Approach 2:
The patent dynamically changes the voltage parameter on the auxiliary select gate line during erase operations. By selectable between different voltage levels based on the erase progress and memory cell state, the system can provide enhanced voltage to cells that are difficult to erase, thereby improving overall erase reliability.
3Measurement precision
If conventional non-volatile memory performs reading operations, then stored data is retrieved, but read accuracy is affected by variations in memory cell characteristics
Solution Approach 1:
During read operations, the auxiliary select gate line provides localized voltage control to ensure consistent read conditions across different memory cells. By compensating for cell characteristic variations through targeted voltage application, the system improves read accuracy and reduces errors caused by manufacturing variations.
4Productivity
If auxiliary select gate line driver is added to non-volatile memory, then programming, erasing, and reading efficiencies are improved, but device complexity increases
Solution Approach 1:
The auxiliary select gate line driver is designed with multi-functionality, serving programming, erasing, and reading operations through a single unified circuit. This universal design improves productivity across all operations while minimizing the increase in device complexity by avoiding separate dedicated circuits for each function.
Solution Approach 2:
The driver circuit utilizes selectable voltage levels (0V, Vpp, Vcc) that can be dynamically changed based on the operation mode. This parameter flexibility allows a relatively simple circuit structure to achieve complex control requirements, improving efficiency without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The auxiliary select gate line driver improves programming efficiency, erasing efficiency, and reading efficiency by adapting to varying memory cell characteristics, reducing program and erase failures.
Implementation Method 1
the auxiliary select gate line driver is connected with a first auxiliary select gate line and a second auxiliary select gate line... a first driving voltage is provided to the first auxiliary select gate line by the auxiliary select gate line driver
Implementation Method 2
the word line driver receives the decoded signal and is connected with the first word line and the second word... the word line driver activates one of the first word line and the second word according to the decoded signal
Data Source
AI summary
A non-volatile memory with an auxiliary select gate line driver is provided. The array structure of the non-volatile memory comprises plural 2T2C memory cells in an array arrangement. The memory cells in the array structure are connected with the corresponding auxiliary select gate lines. The auxiliary select gate line driver can output specified driving voltages to the auxiliary select gate lines. Consequently, the programming efficiency, the erasing efficiency and the reading efficiency of non-volatile memory are enhanced.