Auxiliary Gate Electrodes for Field Effect Source Drain Induction

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Solution Overview

Problem

Semiconductor devices require high data processing capacity and integrity, necessitating the use of thin semiconductor layers instead of bulk substrates, but existing technologies struggle to effectively induce field effect type source/drain regions without doping, which is crucial for efficient operation.

Innovation Solution

The implementation of auxiliary gate electrodes and a semiconductor layer configuration that induces field effect type source/drain regions without impurity doping, using a primary gate electrode and charge storage layer, along with alternating auxiliary gate electrodes to create inversion regions for enhanced semiconductor device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a thin semiconductor layer is used instead of a bulk substrate, then data processing capacity and device integrity are improved, but the ability to effectively induce field effect type source/drain regions without doping deteriorates

Engineering Contradiction:
Improvedata processing capacityVSAvoidfield effect type source/drain region induction
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The gate structure is segmented into multiple auxiliary gate electrodes (first auxiliary gate electrode, second auxiliary gate electrode) positioned at different locations beneath the semiconductor layer. Each auxiliary gate electrode independently induces field effect type source/drain regions at different positions, allowing the thin semiconductor layer to achieve proper field effect induction without requiring impurity doping.

Inventive Principle:
Principle #1Segmentation

2Reliability

If auxiliary gate electrodes are added to induce field effect type source/drain regions, then device performance is improved, but device complexity increases

Engineering Contradiction:
Improvefield effect type source/drain region inductionVSAvoidgate electrode structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The auxiliary gate electrodes are merged with the existing gate structure and formed using the same gate electrode pattern formation process. The auxiliary gate electrodes are positioned beneath the semiconductor layer and integrated with the primary gate electrode, allowing multiple functions (inducing field effect type source/drain regions and maintaining gate control) to be achieved through a unified structure rather than separate components.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables the creation of high-integrity semiconductor devices with efficient field effect type source/drain regions, allowing for improved data processing capacity and operation without the need for impurity doping, suitable for both logic and memory devices.

Implementation Method 1

Each of the plurality of auxiliary gate electrodes may be configured to induce a respective field effect type source/drain region in the semiconductor layer between respective adjacent ones of the primary gate electrodes

Methodology Applied
Scientific EffectField effect: Electric Field

Data Source

PatentUS8299520B2Semiconductor devices including auxiliary gate electrodes and methods of fabricating the same
Publication Date: 2012.10.30 SAMSUNG ELECTRONICS CO LTD
  • US8299520B2 patent drawing
  • US8299520B2 patent drawing
  • US8299520B2 patent drawing

AI summary

According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.