Auxiliary Gate Structure for GaN Power Devices
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Solution Overview
Problem
Power semiconductor devices, particularly pGaN gate E-Mode transistors, face challenges in achieving high threshold voltage, low gate leakage current, and a wide gate voltage operation range, leading to issues like unwanted turn-on during off-states and oscillations due to high dV/dt rates, which affect switching performance.
Innovation Solution
The introduction of an integrated auxiliary gate terminal and a pull-down network in GaN power devices, including a high-voltage active GaN device and a low-voltage auxiliary GaN device, where the high-voltage device's gate is connected to the source of the auxiliary transistor, and the auxiliary transistor's gate is connected to the drain, forming a configuration that enhances threshold voltage and reduces oscillations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an integrated auxiliary gate terminal and pull-down network are added to the GaN power device, then the threshold voltage is enhanced and oscillations are reduced, but the device complexity increases
Solution Approach 1:
The gate control function is segmented into two independent parts: the main gate terminal for primary control and the auxiliary gate terminal for threshold voltage enhancement and oscillation suppression. This segmentation allows each terminal to be optimized for its specific function, improving overall reliability while maintaining manageable complexity through functional decomposition
Solution Approach 2:
The auxiliary gate terminal acts as an intermediary element that mediates between the control signal and the main channel, providing additional control authority to enhance threshold voltage and suppress oscillations without directly complicating the main switching path
2Adaptability or versatility
If the auxiliary transistor's gate is connected to the drain and the high-voltage device's gate is connected to the source of the auxiliary transistor, then the operation window is expanded, but the device complexity increases
Solution Approach 1:
The gate connection topology is made dynamic through the pull-down network that can selectively connect or disconnect the auxiliary gate from different potentials based on the operating state. This dynamic reconfiguration allows the device to adapt to different voltage ranges and operating conditions, expanding the operation window while managing complexity through state-dependent connectivity
Solution Approach 2:
The auxiliary gate structure serves multiple functions simultaneously: it enhances threshold voltage, suppresses oscillations, and enables operation across a wider voltage range. This multi-functionality justifies the additional complexity by providing several benefits from a single structural addition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a GaN transistor with a high threshold voltage, reduced gate leakage, and an expanded operation window, preventing turn-on retriggering and oscillations, thereby improving switching performance and reliability.
Implementation Method 1
The use of an AlGaN/GaN heterostructure also allows the formation of a two-dimensional electron gas (2DEG) at the hetero-interface where carriers can reach very high mobility (μ=2000 cm2/(Vs)) values
Implementation Method 2
the piezopolarization charge present at the AlGaN/GaN heterostructure, results in a high electron density in the 2DEG layer
Data Source
AI summary
The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.