Narrow Bezel Array Substrate With Auxiliary Gate Lines
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Solution Overview
Problem
Liquid crystal display devices (LCDs) face challenges in achieving a narrow bezel, particularly in minimizing the non-display areas on the left and right sides, which is essential for modern electronic devices with high demand for thinner designs.
Innovation Solution
The array substrate design includes paired gate lines spaced at specific distances, with auxiliary gate lines and data lines configured to minimize non-display areas by reducing the number of gate driving ICs and PCBs, allowing for a narrower bezel through optimized layout and reduced component placement in non-display areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If gate driving ICs and PCBs are placed in non-display areas to drive the LCD, then the LCD functionality is ensured, but the non-display area width increases resulting in a wide bezel
Solution Approach 1:
The patent moves the gate driving ICs from the traditional planar non-display areas (left/right sides) to the vertical non-display areas (top/bottom sides) of the array substrate. This dimensional repositioning allows the gate signals to be routed vertically along the gate lines rather than horizontally, enabling a significant reduction in the horizontal bezel width while maintaining all necessary driving functions.
Solution Approach 2:
The patent segments the gate driving functionality by placing multiple gate driving ICs at different locations (top and bottom non-display areas) rather than concentrating all driving components in the traditional side non-display areas. This segmentation allows for more flexible signal routing and enables the horizontal bezel to be minimized while still providing adequate space for all required components.
2Length of moving object
If the number of gate driving ICs and PCBs is reduced to minimize non-display areas, then the bezel width is reduced, but the reliability of signal transmission may be compromised
Solution Approach 1:
The patent incorporates auxiliary gate lines that extend into the display area from the non-display areas, establishing preliminary signal pathways before the main gate lines are activated. These auxiliary lines ensure reliable signal transmission by providing backup routes and ensuring proper signal distribution across the display area, even with reduced component placement.
Solution Approach 2:
The auxiliary gate lines act as intermediaries between the gate driving ICs and the main gate lines. They facilitate reliable signal transmission by providing additional connection pathways and ensuring proper electrical contact, thereby maintaining signal integrity despite the reduced number and repositioned location of gate driving ICs.
3Reliability
If auxiliary gate lines are added to contact gate lines through gate contact holes, then the signal distribution is improved, but the manufacturing complexity increases
Solution Approach 1:
The auxiliary gate lines are merged with the existing gate line structure by making them contact the gate lines through gate contact holes that are formed during the standard TFT manufacturing process. This integration allows the auxiliary lines to be manufactured using the same fabrication steps as the main gate lines, minimizing additional manufacturing complexity while improving signal distribution.
Data Source
AI summary
An array substrate for a liquid crystal display device and method of manufacturing the same are provided. The array substrate includes: a plurality of paired gate lines at a first distance from each other at a boundary between adjacent first regions on a substrate, including a display area including a plurality of first regions, each including two adjacent pixel regions, a gate insulating layer on the gate lines and including a gate contact hole exposing each of the gate lines, a plurality of data lines crossing the paired gate lines, the first regions located at each crossing, an auxiliary gate line parallel with the data lines and at a boundary between the two adjacent two pixel regions, and a thin film transistor in each of the pixel regions and connected to corresponding gate and data lines, wherein the auxiliary gate line contacts the corresponding gate line through the hole.