Auxiliary Gate Nonvolatile Memory Structure for Write Current Reduction
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Solution Overview
Problem
Current nonvolatile memory technologies face challenges in improving write efficiency and reducing write current while maintaining compatibility with standard logic CMOS processes.
Innovation Solution
A nonvolatile memory cell structure is introduced, featuring a PMOS storage transistor with a floating gate, an auxiliary gate, and a select transistor, where the auxiliary gate is positioned in close proximity to the floating gate with a gap between them, allowing for reduced write current and enhanced program efficiency by controlling the channel resistance and generating electron-hole pairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional floating gate NVM structure is used, then data storage capability is achieved, but write current is high and program efficiency is low
Solution Approach 1:
The gate structure is segmented into a control gate and an auxiliary gate positioned in close proximity to the floating gate. The auxiliary gate is separated from the floating gate by a gap directly above the channel, allowing independent voltage application to enhance electron-hole pair generation and improve program efficiency while reducing write current requirements.
Solution Approach 2:
The auxiliary gate acts as an intermediary element between the control gate and the floating gate. By applying voltage to the auxiliary gate, electron-hole pairs are generated in the channel region, which facilitates charge trapping in the floating gate during programming, thereby improving program efficiency and reducing the write current needed.
2Length of moving object
If dimensions and tunneling oxide are shrunk, then device scaling is achieved, but operation voltage decreases and write efficiency deteriorates
Solution Approach 1:
The auxiliary gate is positioned specifically in close proximity to the floating gate with a gap directly above the channel region. This localized configuration creates a concentrated electric field in the channel region, generating electron-hole pairs that enhance charge trapping efficiency during programming, thereby maintaining or improving write efficiency despite reduced tunneling oxide thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively reduces write current and improves program efficiency by controlling the channel resistance and increasing electron-hole pair generation, thereby enhancing the write performance of nonvolatile memory cells.
Implementation Method 1
improving program efficiency by controlling the channel resistance and generating electron-hole pairs
Data Source
AI summary
A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.