Auxiliary Parity Bits for Multi-Level Cell Flash Memory Interruption
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Solution Overview
Problem
In multi-level cell flash memory systems, writing data in multiple passes or portions can be interrupted due to power failures or other interruptions, making reliable decoding difficult, and using a cache to mitigate this issue adds wear to the memory device and reduces writing rate.
Innovation Solution
Generating and writing auxiliary parity bits in a separate region of the memory device, which can be used for decoding if the writing process is interrupted, and discarding them once the data is reliably written to ensure efficient use of memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written in multiple passes or portions to MLC flash memory, then reliability of data storage is improved, but writing rate decreases and risk of interruption increases
Solution Approach 1:
The system performs preliminary writing of data in the first pass, then writes auxiliary parity bits based on the preliminarily written data. This preliminary action allows the auxiliary parity bits to be generated and stored before the second pass, enabling potential data recovery if interruption occurs between passes.
Solution Approach 2:
Auxiliary parity bits serve as an intermediary mechanism between the data written in the first pass and the second pass. These auxiliary parity bits can mediate data recovery if the writing process is interrupted, bridging the gap between incomplete writing stages.
2Reliability
If a cache is used to store data during multiple pass writing, then data retrieval reliability is improved, but memory wear increases and device lifespan decreases
Solution Approach 1:
The auxiliary parity bits are designed as temporary, disposable protection mechanisms. They are written in the first pass, used to protect data during the second pass, and then discarded after the second pass completes successfully. This disposable approach provides protection without the long-term wear associated with cache memory.
Solution Approach 2:
The system discards the auxiliary parity bits after they have served their protective function following the second pass. This discarding mechanism eliminates the need for long-term retention of protection data, reducing wear on memory structures while maintaining reliability during the critical multi-pass writing process.
3Reliability
If auxiliary parity bits are written in a separate region, then data decoding capability during interruption is improved, but memory space consumption increases
Solution Approach 1:
The system writes auxiliary parity bits that provide excessive protection capability for the first pass data. This partial/excessive action ensures that even if interruption occurs, sufficient information exists for potential data recovery, while the auxiliary parity bits occupy only a portion of the total memory space rather than requiring full cache allocation.
Data Source
AI summary
Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where the auxiliary parity bits are computed based on the data bits. Subsequent to writing the data bits a first time and writing the auxiliary parity bits, the data bits are written a second time into the memory. Writing the data bits the first time and writing the data bits the second time are directed to one or more storage elements at a common physical address in the memory. Subsequent to writing the data bits the second time, the auxiliary parity bits are discarded while maintaining the data bits in the memory.