Auxiliary Processor Link Board for Symmetric Multi-Socket Routing

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Solution Overview

Problem

As computer technology advances with increasing core counts and memory requirements, processor-to-processor communication in multi-processor systems consumes a high number of socket pins, leading to design complexities, increased costs, and power consumption, while existing solutions complicate routing and require expensive materials.

Innovation Solution

Implementing an auxiliary circuit board that directly couples processors without using interconnects of the main circuit board, utilizing edge connectors and ultra-low loss materials to facilitate high-speed processor-to-processor communication, reducing the need for socket pins and allowing separate routing of signaling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If processor-to-processor communication uses socket pins on the main circuit board, then communication is enabled, but the number of required socket pins increases, leading to design complexity and increased costs

Engineering Contradiction:
Improveprocessor-to-processor communication capabilityVSAvoidbaseboard design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the communication function into two separate paths: socket pins are used only for processor-to-memory communication, while a dedicated interconnect structure handles processor-to-processor communication. This segmentation eliminates the need for additional socket pins for peer-to-peer communication, reducing overall complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an interconnect structure as an intermediary component that directly couples processor packages without requiring socket pin connections through the baseboard. This intermediary structure simplifies the baseboard design by removing the need for complex routing layers and expensive materials

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If more socket pins are used for multi-socket communication, then communication capability is improved, but manufacturing costs and power consumption increase

Engineering Contradiction:
Improvemulti-socket communication capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments communication functions to use existing socket pins only for processor-to-memory communication, while dedicated interconnect structures handle processor-to-processor communication. This eliminates the need for additional expensive socket pins and complex baseboard materials

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interconnect structure provides a simplified copy or alternative path for processor communication that doesn't require the expensive materials and complex routing of traditional baseboard designs, reducing manufacturing costs

Inventive Principle:
Principle #26Copying

3Reliability

If socket pins are used for processor communication, then communication is enabled, but the number of layers and materials in the baseboard must increase, increasing power consumption

Engineering Contradiction:
Improveprocessor communication capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent separates communication paths so that the dedicated interconnect structure handles processor-to-processor communication with shorter signal paths and fewer layers, reducing power consumption compared to routing through the main baseboard

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3786762B1System, apparatus and method for providing a symmetric multi-processor high-speed link
Publication Date: 2025.07.02 INTEL CORP
  • EP3786762B1 patent drawingFigure 1~2
  • EP3786762B1 patent drawingFigure 3
  • EP3786762B1 patent drawingFigure 4

AI summary

In one embodiment, a circuit board includes: a plurality of layers including interconnects to carry processor-to-processor signaling between a first processor and a second processor; a first connector adapted to a first peripheral portion of the circuit board to couple to a first contact member of the first processor; and a second connector adapted to a second peripheral portion of the circuit board to couple to a first contact member of the second processor. Other embodiments are described and claimed.