Auxiliary Segments Reduce Signal Delay in LCD Array Substrates

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional LCD devices experience signal delay and low charging rates due to parasitic capacitance generated by overlapping scan and data lines, which affects the display effect.

Innovation Solution

Incorporating auxiliary segments that form capacitive coupling with scan and data lines to reduce signal delay, improving charging rates and display performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If scan lines and data lines are overlapped to increase pixel density, then resolution is improved, but parasitic capacitance increases causing signal delay

Engineering Contradiction:
ImproveresolutionVSAvoidsignal delay
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent introduces auxiliary segments as intermediary conductive structures that couple scan lines and data lines through capacitive coupling. These auxiliary segments act as mediators to transfer signals while reducing the direct parasitic capacitance between overlapping scan and data lines, thereby decreasing signal delay while maintaining high resolution

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the electrical parameters by introducing auxiliary segments with specific capacitance values to compensate for the parasitic capacitance effects. By adjusting the capacitance parameters of the auxiliary segments, the signal transmission characteristics are optimized to reduce delay while preserving the overlapping line structure for high resolution

Inventive Principle:
Principle #35Parameter changes

2Speed

If pixel size is reduced to increase charging rate, then response time is improved, but signal delay increases due to overlapping lines

Engineering Contradiction:
Improvecharging rateVSAvoidsignal delay
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The auxiliary segments serve as intermediary elements that facilitate faster signal transfer to reduced-size pixels by providing capacitive coupling paths that bypass the parasitic capacitance bottlenecks, enabling higher charging rates even with smaller pixel dimensions

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If scan lines and data lines overlap extensively to increase pixel density, then display resolution is improved, but display effect deteriorates due to signal delay

Engineering Contradiction:
Improvedisplay resolutionVSAvoiddisplay effect
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The auxiliary segments act as intermediary structures that maintain the high pixel density achieved through line overlapping while simultaneously improving signal transmission reliability. The capacitive coupling provided by auxiliary segments ensures accurate signal delivery to each pixel, preserving display quality despite the dense line configuration

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The capacitive coupling with auxiliary segments effectively reduces signal delay and enhances the pixel charging rate, resulting in improved display quality.

Implementation Method 1

the scan lines and/or data lines forming capacitive coupling with corresponding auxiliary segments to reduce signal delay on the scan lines and/or data lines

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS10365526B2Array substrate, manufacturing method thereof, and display device
Publication Date: 2019.07.30 SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
  • US10365526B2 patent drawing
  • US10365526B2 patent drawing
  • US10365526B2 patent drawing

AI summary

An array substrate, manufacturing method thereof and display device are provided. The array substrate includes a plurality of scan lines, a plurality of data lines intersecting with the plurality of scan lines to as to define a plurality of pixel areas; a plurality of auxiliary segments, and each scan line and/or each data line respectively corresponding to at least a auxiliary segment, the scan line and/or data line and the corresponding auxiliary segment forming capacitive coupling to reduce signal delay on the scan line and/or data line. As such, the signal delay on the scan line and/or data line is reduced, and the charging rate and display effect are improved.