Auxiliary Spacers in Semiconductor Source/Drain Regions

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Solution Overview

Problem

As semiconductor devices are scaled down, the integration of MOSFETs leads to degraded characteristics, necessitating improved manufacturing methods to enhance performance and reliability.

Innovation Solution

The semiconductor device design includes distinct regions with specific active patterns, gate structures, and source/drain regions, featuring auxiliary spacers and epitaxial layers to optimize geometry and material distribution, with varying widths and slopes to improve epitaxial growth and device reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If MOSFETs are scaled down to increase integration, then device density increases, but device characteristics are degraded

Engineering Contradiction:
Improvedevice integration densityVSAvoiddevice characteristics
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The source/drain region is divided into multiple segments along the channel length, including lightly-doped extension regions, heavily-doped main regions, and intermediate regions. This segmentation allows each region to be independently optimized for different functions: extensions provide gradual doping transitions to reduce short-channel effects, while main regions provide strong carrier injection, thereby maintaining device characteristics at scaled dimensions

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different doping concentrations and profiles are applied to different spatial locations within the source/drain structure. The extension regions near the channel have lower doping concentrations to reduce field effects, while regions farther from the channel have higher doping concentrations for efficient carrier supply. This local quality variation enables the device to maintain performance despite overall scaling

Inventive Principle:
Principle #3Local quality

2Reliability

If source/drain regions are heavily doped to improve carrier injection, then conductivity increases, but dopant diffusion causes junction migration and short-channel effects

Engineering Contradiction:
Improvecarrier injection efficiencyVSAvoidjunction position control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Lightly-doped extension regions are formed in the source/drain areas before the main channel formation and before heavy doping of the main source/drain regions. These pre-formed extensions create a doping profile that gradually transitions from the substrate, which prevents excessive field effects and reduces dopant diffusion into the channel during subsequent processing steps, thereby maintaining junction position precision

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The source/drain structure employs a composite doping profile combining lightly-doped and heavily-doped regions in a single continuous structure. This composite approach allows the lightly-doped extensions to act as diffusion barriers while the heavily-doped main regions provide high carrier concentration, resolving the contradiction between conductivity and junction control

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the reliability and performance of semiconductor devices by optimizing the geometry and material distribution, particularly through improved epitaxial growth, preventing connection between source/drain regions and ensuring uniformity, thus addressing the challenges of scaling down MOSFETs.

Implementation Method 1

improved epitaxial growth

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS9412731B2Semiconductor device
Publication Date: 2016.08.09 SAMSUNG ELECTRONICS CO LTD
  • US9412731B2 patent drawing
  • US9412731B2 patent drawing
  • US9412731B2 patent drawing

AI summary

Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.