Auxiliary Substrate Semiconductor Package for Shorter Signal Routing
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Solution Overview
Problem
The incorporation of multiple layers in semiconductor packages leads to increased thickness, posing challenges in applications with space constraints while also affecting signal parasitic degradation and overall circuit performance.
Innovation Solution
Incorporating an auxiliary substrate over the primary substrate to reduce the layer count and maintain or improve trace lengths, thereby reducing package thickness and enhancing performance thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple layers are incorporated in semiconductor packages to maintain trace lengths and reduce parasitic degradation, then circuit performance is improved, but package thickness increases
Solution Approach 1:
The patent introduces an auxiliary substrate positioned between the primary substrate and the semiconductor die, creating an additional dimensional layer for trace routing. This allows signals to travel through multiple substrates in a stacked configuration, effectively reducing the horizontal trace length on any single layer while managing the vertical thickness through optimized layer stacking and selection of low-profile interconnect structures.
Solution Approach 2:
The patent divides the signal path into multiple segments by introducing an auxiliary substrate with its own trace layers. Instead of having long traces on a single substrate, the signal is segmented and routed through the primary substrate, then through the auxiliary substrate, and finally to the die. This segmentation reduces parasitic degradation by breaking up long trace paths into shorter segments across multiple layers.
2Adaptability or versatility
If multiple layers are incorporated in semiconductor packages, then trace routing flexibility is improved, but device complexity increases
Solution Approach 1:
The auxiliary substrate adds a vertical dimension to the trace routing architecture, allowing signals to switch layers and route through different substrates. This third dimension (vertical stacking) provides enhanced routing flexibility without requiring excessive lateral space or complex planar trace patterns, thereby improving adaptability while controlling complexity through vertical rather than horizontal expansion.
Solution Approach 2:
The auxiliary substrate acts as an intermediary layer between the primary substrate and the semiconductor die, providing additional trace routing capabilities. This intermediate layer serves as a mediator that enables complex signal routing patterns by allowing traces to be distributed across multiple substrates, thereby increasing flexibility while managing overall device complexity through functional decomposition.
Data Source
AI summary
Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first substrate having first electrical traces and a second substrate having second electrical traces, where the second electrical traces are electrically coupled with the first electrical traces using at least one wire bond. The semiconductor device assembly includes an integrated circuit between the first substrate and the second substrate, where the integrated circuit is electrically coupled with the first electrical traces using at least one conductive structure.