Auxiliary Test Device Connection Tree for Memory Testing
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Solution Overview
Problem
Conventional memory test methods require new equipment as semiconductor device performance improves and functions change, necessitating a more efficient and adaptable testing solution.
Innovation Solution
A test board and auxiliary test device utilizing a built-out self-test (BOST) technique, with a connection tree structure that includes multiple auxiliary test devices to generate test patterns and clocks, and communicate test results, allowing for serial, binary-tree, ring-network, or two-lane connections to external apparatuses like ATE or PCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional ATE test equipment is used to test memory devices, then test coverage can be achieved, but new equipment is required as semiconductor device performance improves and functions change
Solution Approach 1:
The test system is divided into multiple auxiliary test devices distributed across different locations in the memory device, with each device handling specific test functions. This segmentation allows the system to adapt to different device configurations without requiring complete redesign of the entire test equipment.
Solution Approach 2:
The auxiliary test devices are designed with universal functionality to handle various test operations including pattern generation, clock signal generation, and error detection. This multi-functionality enables the same test system to accommodate evolving semiconductor device performance and different memory device types.
2Productivity
If test patterns are generated using pattern generator with ALPG, then defective passive components can be detected, but test operating speed is limited by equipment capabilities
Solution Approach 1:
Auxiliary test devices serve as intermediaries between the external test equipment and the memory device under test. These intermediary devices generate high-frequency test clocks and patterns locally, enabling faster test operations while maintaining pattern accuracy through dedicated test logic circuits.
3Productivity
If multiple DUTs are tested simultaneously, then testing efficiency improves, but channel constraints and signal integrity become problematic
Solution Approach 1:
The test system segments test operations across multiple auxiliary test devices, each handling specific DUTs or test functions. This segmentation distributes the testing load and reduces channel constraints by parallelizing test operations across multiple independent test paths.
Solution Approach 2:
Auxiliary test devices act as intermediary components that buffer and manage signal paths between DUTs and external equipment. These intermediaries reduce signal interference and channel constraints by providing isolated test paths and proper signal conditioning for each DUT.
Data Source
AI summary
The test board may include sockets in which a plurality of devices-under-test (DUTs) is inserted, and an auxiliary test device connection tree electrically connected to the sockets. The auxiliary test device connection tree includes at least one first auxiliary test device receiving and outputting a test request from an external apparatus, and at least one second auxiliary test device generating a test clock and a test pattern in response to the test request outputted from the at least one first auxiliary test device, performing a test operation about at least one among the DUTs using the generated test pattern, and outputting whether or not of an error of the test operation to the at least one first auxiliary test device.