Page Buffer Circuit Layout With Auxiliary Wires for Coupling Control
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Solution Overview
Problem
As memory devices become more integrated, the complexity of operating circuits and wiring structures increases, necessitating a reduction in page buffer circuit size while maintaining electrical performance and optimizing wire layout.
Innovation Solution
The layout of wires in the page buffer circuit is redesigned to include transistors with specific arrangements of connection wires and auxiliary wires that act as capacitors, preventing capacitive coupling and increasing the capacitance of sensing nodes, thereby improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of the page buffer circuit is reduced to increase the degree of integration, then the area occupied by the page buffer circuit is reduced, but the wire layout becomes more complicated and electrical characteristics deteriorate
Solution Approach 1:
The page buffer circuit is divided into multiple page buffer units, each handling specific bit lines. This segmentation allows independent optimization of each unit's wire layout, reducing overall complexity while maintaining compact area. Each unit processes a subset of data, enabling modular design that scales efficiently.
Solution Approach 2:
Connection wires are arranged in multiple layers (first connection wires in one layer, second connection wires in another layer) to reduce planar complexity. This three-dimensional wire routing approach allows wires to cross without interference, simplifying the two-dimensional layout while maintaining electrical performance.
2Area of moving object
If the size of semiconductor elements is reduced to increase integration, then the area of transistors is reduced, but wire layout becomes more complicated and performance may deteriorate
Solution Approach 1:
Different regions of the page buffer circuit employ different wire routing strategies optimized for local requirements. For example, wires connecting to sensing nodes use specific routing patterns different from those connecting to cache units, allowing each region to be optimized independently for its functional requirements.
Solution Approach 2:
The connection wire structure is designed to serve multiple functions: first connection wires provide primary electrical connections, while also serving as part of the capacitive coupling prevention structure. Second connection wires provide additional routing paths and contribute to overall circuit functionality, reducing the need for dedicated separate structures.
3Speed
If wire length is reduced to improve speed, then signal transmission time is reduced, but capacitive coupling between adjacent wires increases
Solution Approach 1:
Ground wires are introduced as intermediary elements between signal-carrying connection wires. These ground wires act as shields that intercept and divert capacitive coupling effects, preventing them from interfering with signal integrity. The ground wires maintain close proximity to signal wires without requiring increased spacing, thus preserving compact design while eliminating harmful coupling.
Solution Approach 2:
Wires are routed in different vertical layers rather than being confined to a single plane. This three-dimensional arrangement reduces parasitic capacitance between adjacent wires by increasing their physical separation in the vertical dimension, while maintaining short horizontal paths for fast signal transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This redesign enhances the reliability of memory devices by reducing voltage variations at sensing nodes, improving data input/output speed, and maintaining performance despite reduced wire lengths.
Implementation Method 1
a first auxiliary wire extending in the first direction and disposed between adjacent first connection wires
Implementation Method 2
at least some of the plurality of first connection wires are respectively connected with the source, the drain, and the gate electrode through a plurality of first contacts
Data Source
AI summary
A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected with the memory cells through a plurality of bit lines. A sensing node is connected to a bit line for each buffer circuit. The plurality of page buffer units are respectively connected with sensing nodes, each of the plurality of page buffer units includes at least one transistor. One or more auxiliary wires in the proximity of the sensing node are used to reduce coupling problems caused by a low capacitance of the sensing node.