Avalanche Capability Improvement in Power Semiconductor Devices
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Solution Overview
Problem
Conventional power semiconductor devices suffer from poor avalanche capability due to parasitic bipolar transistor triggering near the bottom of trenched gates, leading to hazardous conditions and reduced device performance.
Innovation Solution
The implementation of a power semiconductor device structure with a plurality of trench MOSFETs featuring an epitaxial layer with a lower doping concentration, a doped poly-silicon gate layer, and an avalanche capability enhancement doped region underneath the body ohmic contact doped region, which shifts the avalanche current away from the gate trenches and enhances UIS current while maintaining breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p+ body ohmic contact doped region is implanted surrounding the bottom of the trenched source-body contact structure to decrease contact resistance, then the contact resistance between the P body regions and the contact structure is reduced, but the parasitic bipolar transistor is easily triggered turning on due to high resistance underneath the n+ source regions, weakening the avalanche capability
Solution Approach 1:
The patent introduces an avalanche capability enhancement doped region with specific doping concentration and depth parameters (e.g., 1E13 to 1E15 atoms/cm², 0.5-2.0 micrometers deep) located specifically underneath the n+ source regions. This localized doping modification creates different electrical properties in different areas: the enhancement region provides low resistance paths to prevent parasitic transistor triggering, while the overall device structure maintains its breakdown voltage characteristics.
Solution Approach 2:
The patent modifies the doping concentration and depth parameters of the body region to create the avalanche capability enhancement doped region. By controlling the doping dose (1E13 to 1E15 atoms/cm²) and implantation energy (50-200 keV), the patent optimizes the resistance characteristics to prevent parasitic bipolar transistor triggering while maintaining avalanche capability. The enhancement region has higher doping concentration than the surrounding body region, creating a gradient that manages current flow.
2Ease of manufacture
If the sidewalls of the trenched source-body contact structure are made perpendicular to the front surface to simplify manufacturing, then the fabrication process is simplified, but the p+ body ohmic contact doped region can only be formed surrounding the bottom, resulting in high resistance underneath the n+ source regions
Solution Approach 1:
The patent maintains the simple perpendicular sidewall structure for manufacturing ease, but compensates for the electrical performance issue by introducing a localized enhancement doped region underneath the n+ source regions. This local modification addresses the high resistance problem without requiring complex contact structure geometries, thus preserving manufacturing simplicity while improving avalanche capability.
Solution Approach 2:
The avalanche capability enhancement doped region acts as an intermediary layer between the n+ source regions and the P body regions. This intermediate doped region provides a low-resistance path that compensates for the limitations of the simple perpendicular contact structure, enabling good electrical connection without complex geometry.
3Ease of manufacture
If ion implantation is performed through a contact opening and filling with a W plug for formation of the trenched source-body contact structure, then the contact structure is formed, but the p+ body ohmic contact doped region is formed only surrounding bottom, resulting in high resistance Rb underneath the n+ source regions
Solution Approach 1:
The patent performs ion implantation for the avalanche capability enhancement doped region at a specific stage in the manufacturing process, before final contact structure completion. This preliminary doping action ensures that the enhancement region is in place before subsequent processing steps, allowing precise control over the doped region's depth and concentration without interference from later manufacturing steps.
Solution Approach 2:
The patent uses controlled ion implantation parameters (doping dose, energy, and angle) to precisely position and concentrate the enhancement doped region underneath the n+ source regions. By adjusting implantation energy (50-200 keV) and dose (1E13 to 1E15 atoms/cm²), the patent achieves the desired doping profile with high manufacturing precision, creating a localized low-resistance path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents parasitic bipolar transistor triggering and enhances avalanche capability, improving the overall performance of power semiconductor devices by shifting avalanche occurrence and increasing UIS current with minimal impact on breakdown voltage.
Implementation Method 1
avalanche always occurs near bottom of the trenched gates 110, causing a hazardous condition to the power semiconductor device
Implementation Method 2
a p+ body ohmic contact doped region 116 is implanted surrounding bottom of the trenched source-body contact structure 118
Data Source
AI summary
A power semiconductor device with improved avalanche capability is disclosed by forming at least one avalanche capability enhancement doped region underneath an ohmic contact doped region. Moreover, a source mask is saved by using three masks process and the avalanche capability is further improved.