Avalon to Axi4 Bus Conversion via Asynchronous FIFO
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Solution Overview
Problem
Current FPGA engineering designs face inefficiencies due to the need to support multiple bus protocols like Avalon and Axi4, which prolong development cycles and require complex interface modifications, with existing solutions like amm_axi_bridge being limited to specific platforms and not supporting cross-clock-domain conversion.
Innovation Solution
An Avalon-to-Axi4 bus conversion method that performs logical processing on Avalon_st bus data for delay-free conversion and frames and stores Avalon_mm bus signals in asynchronous FIFO for cross-clock-domain conversion, enabling rapid interface design and matching across platforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple bus protocols (Avalon and Axi4) are supported in FPGA engineering designs, then platform compatibility is improved, but development cycle is prolonged and interface complexity increases
Solution Approach 1:
The patent introduces an intermediary conversion module that translates between Avalon bus protocol and Axi4 bus protocol. This mediator handles protocol conversion internally, allowing the system to support multiple platforms without requiring separate interface implementations for each protocol, thereby reducing development cycle while maintaining platform compatibility.
Solution Approach 2:
The conversion module is designed with universal functionality to handle both Avalon-to-Axi4 and Axi4-to-Avalon conversions, as well as support for both synchronous and asynchronous bus modes. This multi-functional design eliminates the need for separate conversion modules for each protocol direction and mode, reducing overall development time and complexity.
2Ease of manufacture
If existing conversion IP (amm_axi_bridge) is used, then conversion functionality is provided, but platform limitation and cross-clock-domain conversion support are worsened
Solution Approach 1:
The conversion module is segmented into independent functional units: protocol parsing layer, conversion logic layer, and protocol output layer. Each layer handles specific conversion tasks independently, allowing the module to be configured for different platforms and clock domains without affecting other parts, thereby improving adaptability while maintaining conversion functionality.
Solution Approach 2:
The conversion module employs dynamic clock domain handling mechanisms that automatically adapt to different clock domain configurations. The module can dynamically adjust its operation mode based on whether synchronous or asynchronous clock domains are detected, enabling cross-clock-domain conversion support while maintaining ease of implementation.
3Adaptability or versatility
If Avalon_mm bus signals are converted to Axi4 bus, then memory mapping functionality is improved, but cross-clock-domain conversion capability is worsened without asynchronous FIFO
Solution Approach 1:
An asynchronous FIFO structure is introduced as an intermediary buffer between the Avalon_mm bus interface and the Axi4 bus interface. This mediator decouples the two clock domains, allowing reliable data transfer even when the source and destination operate at different clock frequencies, thereby improving cross-clock-domain conversion reliability while maintaining memory mapping functionality.
Data Source
AI summary
Disclosed is an Avalon-to-Axi4 bus conversion method, including: in case that an Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, performing a logical process on the received Avalon_st bus data, and then outputting corresponding Axi4_st bus data; and in case that the Avalon bus is an Avalon_mm bus, receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus.