Avionics Startup Sequencing via Criticality-Based Execution

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Solution Overview

Problem

Electronic avionics systems on airborne platforms face challenges in ensuring safe operation and meeting design assurance levels during startup, particularly in dynamic conditions, due to the complexity and number of computational tasks required.

Innovation Solution

A control circuit with multiple processing cores integrated in a single chip assembly, coupled to a memory device via an electronic bus, which includes an avionics circuit, configuration circuit, and sequencing circuit. The configuration circuit assigns criticality indications to avionics instructions, and the sequencing circuit generates an execution sequence to prioritize critical instructions, ensuring timely and safe startup of avionics systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If multiple avionics instructions are executed in parallel using multicore processors, then the total startup time is reduced, but it becomes difficult to ensure safe operation and meet design assurance level requirements

Engineering Contradiction:
Improveavionics startup timeVSAvoiddesign assurance level compliance
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent segments avionics instructions into different criticality groups (critical, important, non-critical) and assigns them to different processing cores or execution queues. This segmentation allows parallel execution of multiple instructions while maintaining proper prioritization and ensuring that critical instructions receive the necessary attention to meet design assurance requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by assigning different execution characteristics to different instructions based on their criticality. Critical instructions are executed with higher priority, stricter timing constraints, and potentially dedicated processing resources, while non-critical instructions can be executed with more relaxed constraints. This ensures that safety-critical functions meet design assurance levels while overall startup time is reduced through parallel execution of non-critical functions.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If the number of electronic applications in avionics systems increases to meet growing feature requirements, then system functionality is improved, but the complexity of ensuring safe operation during startup increases

Engineering Contradiction:
Improveavionics system functionalityVSAvoidstartup control complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal startup control architecture that can handle any number and type of avionics applications through a standardized criticality-based execution framework. The system uses a universal instruction format with criticality indicators that can be applied to diverse avionics functions, allowing the system to scale in functionality without proportionally increasing startup control complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent manages complexity by changing the parameter of instruction criticality rather than creating complex control logic for each individual application. By assigning criticality parameters to instructions and using these parameters to drive execution priority and resource allocation, the system can accommodate growing functionality while maintaining manageable startup control through parameter-based rather than structure-based complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10088843B1Systems and methods for configurable avionics start sequencing
Publication Date: 2018.10.02 ROCKWELL COLLINS INC
  • US10088843B1 patent drawing
  • US10088843B1 patent drawing
  • US10088843B1 patent drawing

AI summary

A control circuit includes a plurality of processing circuits integrated in a single chip assembly and coupled to a memory device via an electronic bus. At least a first processing circuit is configured to execute avionics instructions independent of at least a second processing circuit. The memory device includes an avionics circuit, a configuration circuit, and a sequencing circuit. The avionics circuit includes a plurality of avionics instructions that when executed control operation of avionics systems in an airborne platform. The configuration circuit includes a plurality of criticality indications corresponding to the plurality of avionics instructions. The sequencing circuit is configured to generate a sequence for execution of avionics instructions based on the plurality of criticality indications to satisfy a system requirement for operation of the airborne platform, and cause the plurality of processing circuits to execute the plurality of avionics instructions according to the sequence.