Adaptive Voltage Scaling Scanning for SoC Power Optimization
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Solution Overview
Problem
Conventional adaptive voltage scaling methods require extensive time during mass production and testing, and the AVS look-up tables established in these environments may not be suitable for the final electronic product due to environmental discrepancies, leading to inefficient power management and increased power consumption.
Innovation Solution
An adaptive voltage scaling scanning method that enables a System on Chip (SoC) to read a boot code from a storage unit and perform AVS scanning after being mounted on a printed circuit board, determining target supply voltages for various operating frequencies to establish a look-up table, which is then stored for future use, ensuring optimal power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If AVS scanning is performed during mass production and testing, then the AVS look-up table can be established, but it requires extensive time and the environment differs from the final product, making the table unsuitable
Solution Approach 1:
The patent performs AVS scanning during the first-time boot-up of the SoC in the final product environment, before normal operation begins. This preliminary action establishes the AVS look-up table under actual operating conditions (temperature, voltage, frequency) that match the final product, ensuring accuracy without requiring separate production-time testing.
Solution Approach 2:
The system automatically performs AVS scanning and establishes the look-up table autonomously during initial boot-up, without requiring external testing equipment or manual intervention. The SoC uses its own resources (CPU, memory, power supply) to complete the scanning process, eliminating the need for time-consuming production line testing.
2Reliability
If a same supply voltage is utilized for both high speed chip and low speed chip, then the low speed chip can operate normally, but the high speed chip experiences increased leakage current and power consumption
Solution Approach 1:
The patent creates individualized AVS look-up tables for each SoC based on its specific performance characteristics (high speed or low speed). This local customization allows each chip to receive the precise supply voltage it needs for its speed class, rather than applying a uniform voltage to all chips. High speed chips receive lower voltages to reduce leakage, while low speed chips receive appropriate voltages to ensure reliable operation.
Solution Approach 2:
The system dynamically adjusts the supply voltage parameter based on the chip's actual performance measured during boot-up. By changing the voltage parameter according to each chip's speed characteristics and storing this in its dedicated look-up table, the system optimizes power consumption while maintaining reliability for each individual chip.
Data Source
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AI summary
The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) (120) on a printed circuit board (PCB) (102), and connecting the SoC (120) to a storage unit (130); enabling the SoC (120) to read a boot code from the storage unit (130), and executing the boot code to perform an AVS scanning operation on the SoC (120) to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC (120) to establish an AVS look-up table; and storing the AVS look-up table into the SoC (120) or the storage unit (1 30).