AVSS Controlled Flash Memory Programming via Floating Gate Feedback
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Solution Overview
Problem
The program margin in Flash memory cells decreases over time due to wear-out mechanisms, leading to unreliable cell reading, especially in two-transistor configurations, where existing control methods for the floating gate potential are inadequate.
Innovation Solution
A method and apparatus that utilize a voltage comparator and capacitive coupling ratios to regulate the floating gate potential during programming and erase operations, allowing for direct measurement and control of the floating gate potential, thereby limiting electrical stress and maintaining a stable program margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional control methods are used for floating gate potential, then programming operation can be performed, but the program margin decreases over time due to wear-out mechanisms
Solution Approach 1:
The patent implements feedback control by monitoring the source line potential (which directly reflects floating gate potential through capacitive coupling) and using this information to regulate the programming operation. The voltage comparator compares the source line potential against a reference voltage and adjusts the programming pulse duration accordingly, ensuring the floating gate potential reaches but does not exceed the target threshold, thereby maintaining stable program margin over extended operating lifetime.
Solution Approach 2:
The patent replaces direct measurement of floating gate potential with an electrical field-based indirect measurement through the voltage comparator monitoring source line potential. This substitution allows non-intrusive measurement and control of the floating gate potential without requiring direct physical access to the floating gate, enabling precise control while maintaining device integrity over time.
2Reliability
If floating gate potential is raised sufficiently to achieve adequate Vtp, then programmed state is achieved, but over-programming occurs which reduces program margin
Solution Approach 1:
The feedback mechanism continuously monitors the source line potential and compares it with a reference voltage representing the target floating gate potential. When the source line potential reaches the reference voltage, the feedback signal terminates the programming pulse, ensuring the floating gate potential achieves the exact target value without exceeding it, thereby preventing over-programming and maintaining precise control.
Solution Approach 2:
The patent employs dynamic control by adjusting the programming pulse duration in real-time based on the monitored source line potential. Rather than using a fixed programming pulse width, the system dynamically terminates the pulse when the target potential is reached, adapting to variations in cell characteristics and ensuring precise floating gate potential control for achieving reliable programmed state.
3Manufacturing precision
If direct measurement of floating gate potential is implemented, then precise control is achieved, but device complexity increases
Solution Approach 1:
The patent introduces the source line potential as an intermediary that directly reflects the floating gate potential through known capacitive coupling ratios. By measuring the source line potential instead of the floating gate potential directly, the system achieves precise control while avoiding the complexity of direct floating gate measurement circuits, as the source line is already part of the existing cell structure.
Solution Approach 2:
The source line serves multiple functions: it is used for conventional programming operations and simultaneously serves as a sensing line for monitoring floating gate potential through the voltage comparator. This multi-functionality eliminates the need for separate measurement circuits, reducing overall device complexity while enabling precise floating gate potential control.
Data Source
AI summary
A method for programming a Flash memory array comprises coupling at least one of a current source and a potential source to at least one selected bitline of a Flash memory array, monitoring a potential VAVSS of an array VSS line by means of a comparator, allowing the array VSS line to electrically float until the potential VAVSS is approximately equal to a reference potential Vref, and terminating the programming by de-coupling at least one of the current source and the potential source.