AW2XIP Flash Manager for XIP Read Preemption
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Solution Overview
Problem
Systems on a Chip (SoCs) with limited memory resources face challenges in concurrently performing Execute in Place (XIP) read operations and write operations, leading to significant XIP downtime, increased bill of materials, and additional compute resources due to different transfer modes and prioritization needs.
Innovation Solution
The Adaptive Write While Execute in Place (AW2XIP) circuitry prioritizes real-time XIP read operations over best-effort and write operations, allowing preemption of write operations to minimize downtime by using request queues, write polling, and mode switching to manage concurrent operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the SoC performs write operations to external non-volatile memory, then the memory resources are utilized effectively, but XIP downtime increases significantly
Solution Approach 1:
The flash manager circuitry dynamically switches between write mode and XIP read mode based on incoming requests. When a high-priority XIP read request arrives during a write operation, the system preempts the write operation and switches to read mode, allowing the XIP operation to proceed without significant downtime. This dynamic mode switching resolves the contradiction by making the memory interface adaptable to different operation priorities.
Solution Approach 2:
The system uses request queues to preliminarily organize and prioritize incoming memory operations. By pre-processing requests and identifying high-priority XIP operations before they reach the flash interface, the system can prepare for mode switching in advance, minimizing the disruption to write operations and reducing XIP downtime.
2Productivity
If the SoC implements concurrent write and XIP read operations, then resource utilization improves, but the device complexity increases
Solution Approach 1:
The flash manager circuitry acts as an intermediary between the compute core and the external flash memory. It manages the complexity of concurrent operations by implementing request queues, priority arbitration, and mode switching logic within the flash manager itself, rather than requiring complex control logic in the compute core or memory interface. This intermediary approach enables concurrent operations while containing the complexity in a dedicated management unit.
Solution Approach 2:
The memory management functionality is segmented into distinct components: request queuing, priority arbitration, mode switching, and actual memory operations. This segmentation allows each component to be optimized independently and simplifies the overall control logic by breaking down the complex task of concurrent operation management into manageable, modular functions.
3Speed
If the system prioritizes XIP read operations over write operations, then real-time performance improves, but write operation completion time increases
Solution Approach 1:
The system implements periodic checking of the write operation status and incoming XIP read requests. Instead of allowing a single XIP operation to completely block write operations, the system periodically switches between write and read modes based on request priority and write operation progress. This periodic action ensures that write operations make steady progress while still allowing high-priority XIP operations to proceed with minimal delay.
Data Source
AI summary
An example device includes: a compute core configured to: send a first request to flash manager circuitry, the first request to store write data in a flash memory; and send a second request to the flash manager circuitry, the second request sent after the first request, the second request to transfer an XIP read operation to the flash memory; the flash manager circuitry configured to: receive the first request; transmit the write data to the flash memory for storing in the flash memory; receive the second request before the storing of the write data is complete; determine whether to preempt the storing of the write data, transmit, in response to a determination to preempt, the XIP read operation to the flash; and the flash memory configured to provide data to the compute core based on the transmitted XIP read operation.