AXI Bus Decryption Engine Latency Reduction
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Solution Overview
Problem
Existing decryption techniques introduce latency that is not compatible with high-performance bus operations, particularly in microcontrollers like STM32, which require fast execution of encrypted code and data burst reads with reduced silicon area and latency on 64-bit AXI bus interfaces.
Innovation Solution
A decryption engine based on a finite state machine (FSM) that performs parallel address decoding, generation, and decryption during AES mask mining, utilizing speculative trigger of AES mask generation and AXI burst field extraction to manage response data flow efficiently, thereby reducing latency and area impact on 64-bit AXI bus interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If basic encryption/decryption processing is used, then security is provided, but latency is introduced that is not compatible with high-performance bus operation
Solution Approach 1:
The patent applies preliminary action by pre-generating AES masks and pre-decoding addresses before actual decryption is needed. The system speculatively triggers mask generation and extracts AXI burst fields in advance, so that when decryption is required, the processing can proceed immediately without introducing latency to the high-performance bus operation.
Solution Approach 2:
The decryption process is segmented into multiple parallel operations: address decoding, mask generation, and data decryption are performed as separate concurrent tasks. This segmentation allows each component to be optimized independently and eliminates sequential processing bottlenecks, maintaining high-speed bus operation while providing security.
2Productivity
If decryption processing is performed on high-performance bus, then fast execution is achieved, but silicon area increases
Solution Approach 1:
The patent implements a universal decryption engine that handles multiple decryption scenarios through a single integrated architecture. The finite state machine and AES mask generation circuitry serve multiple purposes: address decoding, mask generation, and coordination with AXI burst operations. This multi-functionality reduces the overall silicon area compared to having separate dedicated circuits for each function.
Solution Approach 2:
The decryption engine is designed to be self-sufficient by integrating all necessary components within the bus interface itself. The system performs speculative mask generation and address decoding autonomously without requiring external assistance, eliminating the need for additional support circuits and reducing overall silicon area while maintaining fast execution.
3Loss of time
If parallel address decoding and mask generation are performed, then latency is reduced, but device complexity increases
Solution Approach 1:
The patent employs a dynamic finite state machine that adapts its behavior based on the current processing stage. The FSM transitions between states to coordinate address decoding, mask generation, and decryption operations dynamically. This dynamic control mechanism allows parallel processing to reduce latency while the state-machine architecture keeps the control logic manageable and avoids excessive circuit complexity.
Data Source
Figure 1
Figure 2~3
AI summary
A method for data decryption comprises receiving (32), over an AXI bus (10) operating in burst mode, data access requests for data units stored in a memory (MC), subdividing the requests received into requests for encrypted data units and requests for non-encrypted data units, forwarding both requests for encrypted data units and requests for non-encrypted data units towards the memory (MC), retrieving the respective sets of data units over the AXI bus (20), and applying Advanced Encryption Standard, AES, processing (60, 70, 80) to the requests for encrypted data units by calculating (72) decryption masks for the encrypted data units and applying (80) the decryption masks calculated to the encrypted data units retrieved. Subdividing the requests into requests for encrypted data units and requests for non-encrypted data units is performed depending on data start addresses and security information conveyed by the requests.