AXI Bus Routing Structure to Reduce NPU Interconnect Congestion
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Solution Overview
Problem
The design of network on chip in AI processing chips faces challenges with high bandwidth requirements, leading to significant congestion due to numerous interconnection buses, especially in multi-core neural network processing units (NPUs) and interactions with on-chip memory.
Innovation Solution
An AXI bus structure is introduced, grouping plural master and slave functional units into groups, sharing routing networks formed by first and second routing units, reducing the number of interconnected buses and alleviating congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of interconnection buses is increased to support high bandwidth requirements in multi-core NPUs and on-chip memory interactions, then data throughput capability is improved, but device complexity and congestion in back-end implementation worsen
Solution Approach 1:
The patent applies merging by consolidating multiple AXI bus interfaces into shared routing networks. Multiple master functional units share common first routing units, and multiple slave functional units share common second routing units, reducing the total number of interconnected buses while maintaining high bandwidth capability through efficient resource sharing
Solution Approach 2:
The routing units are designed with universal functionality to handle data traffic from multiple master functional units and to multiple slave functional units. The first routing units and second routing units serve multiple purposes and multiple functional units, eliminating the need for dedicated point-to-point bus connections for each functional unit pair
2Productivity
If the number of interconnection buses is increased to meet bandwidth requirements, then data interaction capability between functional units is improved, but congestion problem in back-end implementation worsens
Solution Approach 1:
Multiple data paths are merged into shared routing networks with arbitration mechanisms. The first routing units and second routing units handle data interaction for multiple master and slave functional units respectively, combining multiple data flows into organized shared paths that prevent congestion through systematic resource management
Solution Approach 2:
The routing units act as intermediary components between master and slave functional units. Instead of direct point-to-point connections that would require numerous buses, the routing units mediate data transmission, organizing and managing data flows to eliminate congestion while maintaining high interaction capability
Data Source
AI summary
An AXI bus structure and a chip system. The AXI bus structure includes: at least two master functional unit groups, each of which including at least two master functional units; at least two first routing units, being in one-to-one correspondence with the at least two first routing units, and each of the first routing units being respectively connected to each master functional unit of the corresponding master functional unit group by an AXI bus; at least two second routing units, each second routing unit being respectively connected to each first routing unit by an AXI bus; at least two slave functional unit groups, each slave functional unit group including at least two second slave functional units, which being in one-to-one correspondence with the second routing units, and each second routing unit being respectively connected to each slave functional unit of the corresponding slave functional unit group by an AXI bus.