AXI Cipher Engine Mode Switching With Read-Channel Stalling
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Solution Overview
Problem
Existing memory cipher engines face challenges in managing mixed data traffic on an AXI bus, leading to inconsistencies and protocol violations when dynamically switching between stream and block cipher operation modes.
Innovation Solution
A processing system with a cipher engine that selectively operates in stream or block cipher modes, stalling the read data channel during mode switches to ensure consistent data transfer, using dual FIFO registers to manage outstanding transactions and dynamically control the read channel based on the expected cipher mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a cipher engine dynamically switches between stream cipher mode and block cipher mode to handle different data traffic types, then the adaptability and versatility of the system is improved, but protocol violations and data inconsistencies occur on the AXI bus
Solution Approach 1:
The system dynamically switches between stream cipher mode and block cipher mode based on the type of data traffic detected on the AXI bus. The cipher engine can adapt its operation mode in real-time to handle different data patterns, maintaining versatility while managing protocol compliance through dynamic configuration.
Solution Approach 2:
A mode detection and control mechanism acts as an intermediary between the data traffic and the cipher engine. This intermediary detects the data traffic type and automatically configures the appropriate cipher mode, preventing protocol violations by ensuring the cipher engine operates in the correct mode for the current data stream.
2Reliability
If separate cipher engines are used for stream cipher mode and block cipher mode to avoid protocol violations, then the reliability and protocol compliance are improved, but the device complexity and area increase
Solution Approach 1:
A single cipher engine is designed to perform both stream cipher operations and block cipher operations by dynamically configuring its internal logic. This multi-functional approach eliminates the need for separate cipher engines, reducing device complexity and area while maintaining protocol compliance through proper mode management.
Solution Approach 2:
The stream cipher logic and block cipher logic are merged into a single unified cipher engine structure. By combining both cipher types in one engine with a mode selection mechanism, the system avoids duplicating hardware resources, thereby reducing area and complexity while ensuring reliable operation on the AXI bus.
3Manufacturing precision
If data is buffered in a buffer memory for block cipher processing, then the manufacturing precision and data consistency are improved, but the loss of time and processing delay increase
Solution Approach 1:
The data processing is segmented into fixed-size blocks that are buffered and processed sequentially by the block cipher engine. This segmentation ensures data consistency by processing complete blocks, while the buffered approach allows for efficient batch processing that minimizes overall delay compared to byte-by-byte processing.
Solution Approach 2:
Data is pre-buffered in the buffer memory before block cipher processing begins. This preliminary buffering allows the system to collect complete blocks of data in advance, ensuring data consistency for cryptographic processing while enabling parallel preparation of multiple blocks, thereby reducing the impact of processing delays on overall system performance.
Data Source
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AI summary
A processing system (1) comprises a master device (10) and a slave device (20) coupled via an interconnection bus. The master device (10) is configured to issue memory burst transaction requests via the interconnection bus to fetch data from the slave device (20). The system (1) comprises a cipher engine (40) coupled to the interconnection bus and configured to decrypt the data fetched from the slave device (20) to produce plaintext data for the master device (10). The cipher engine (40) selectively operates according to a stream cipher operation mode, wherein a stream of data is fetched from the slave device (20) and processed in a combinatorial circuit (42) to produce the plaintext data, or a block cipher operation mode, wherein a block of data is fetched from the slave device (20), stored in a buffer memory (44) of the cipher engine (40), and processed in a cryptographic engine (41) to produce the plaintext data. The cipher engine (40) is configured to stall a read data channel of the interconnection bus (30) between the slave device (20) and the master device (10) in response to the cipher engine (40) switching from the block cipher operation mode to the stream cipher operation mode. The cipher engine (40) is configured to reactivate the read data channel in response to a last beat of a read burst of the plaintext data produced by the cryptographic engine (41) and corresponding to the block of data stored in the buffer memory (44) being received by the master device (10).