AXI Demultiplexer Transaction Ordering Across Memory Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
On-chip communication systems face challenges in maintaining transaction ordering across multiple memory channels, leading to potential processing delays and errors due to differences in request processing rates among memory channels.
Innovation Solution
An AXI demultiplexer system that determines transaction identifiers and target memory channels, selectively holding transactions to ensure that requests and responses adhere to ordering rules by using a read/write transaction decoder and response module to manage outstanding transactions across multiple memory channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transaction ordering is maintained by tracking identifiers for every outstanding transaction on all outgoing ports, then transaction ordering is preserved, but processing delays occur and memory resources are consumed
Solution Approach 1:
The patent segments the transaction tracking system into separate FIFO buffers for each memory channel instead of using a single comprehensive tracking structure. Each buffer independently tracks transactions for its designated channel, reducing the complexity and resource requirements of global tracking while maintaining ordering guarantees for each channel.
Solution Approach 2:
The patent introduces a new dimension of organization by mapping transactions to specific memory channels through FIFO buffers associated with each channel. This channel-specific dimensional organization eliminates the need for complex cross-channel tracking and reordering logic, thereby reducing processing delays while preserving ordering.
2Reliability
If transaction ordering is maintained by keeping track of identifiers for every outstanding transaction, then transaction ordering is preserved, but memory resources and associated logic are required
Solution Approach 1:
The patent divides the memory resources and tracking logic into separate FIFO buffers for each memory channel. This segmentation reduces the complexity of the overall system by localizing tracking functions to channel-specific structures, eliminating the need for a single complex global tracking mechanism.
Solution Approach 2:
Each FIFO buffer autonomously manages its own transaction tracking and ordering without requiring intervention from a central tracking authority. The buffers self-service by independently monitoring their own outstanding transactions and maintaining order, thereby reducing the overall logic requirements of the system.
3Productivity
If transactions are processed across multiple memory channels without selective holding, then processing speed is improved, but transaction ordering may be violated due to different processing rates
Solution Approach 1:
The patent implements preliminary action by using FIFO buffers to pre-organize transactions for each memory channel before they are dispatched. This preliminary organization ensures that transactions are ready to be processed in the correct order, allowing the system to maintain ordering even when memory channels operate at different speeds, without requiring complex real-time reordering.
Data Source
AI summary
Embodiments are disclosed relating to methods of ordering transactions across a bus of a computing device. One embodiment of a method includes determining a current target memory channel for an incoming transaction request, and passing the incoming transaction request downstream if the current target memory channel matches an outstanding target memory channel indicated by a direction bit of a counter or the counter equals zero. The method further includes holding the incoming transaction request if the counter is greater than zero and the current target memory channel does not match the outstanding target memory channel.