AXI Bus ID Extension for Multi-Crossbar SoC Interconnect
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Solution Overview
Problem
The AXI bus efficiency decreases due to ID information loss when implementing interconnection between multiple on-chip bus structures, leading to non-sequential transmission and reduced efficiency.
Innovation Solution
A system on chip (SoC) and transmission method that adds and subtracts bits from the ID carried in transmission requests and responses to maintain bit width compatibility across interconnection structures, avoiding ID compression and ensuring efficient data transfer between multiple on-chip bus structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cross-connected nodes are interconnected simultaneously in a crossbar structure, then data can be transmitted between multiple master devices and multiple slave devices simultaneously, but the number of AXI bus signal wires increases noticeably leading to difficulty of wiring and consumption of large areas of chips
Solution Approach 1:
The patent divides a large crossbar into multiple small crossbars (first crossbar, second crossbar, etc.). Each small crossbar handles a subset of master devices and slave devices, reducing the signal wire count per crossbar from O(n*m) to O(k*l) where k<n and l<m. The small crossbars are interconnected through loop connections with ID extension modules to maintain system-wide accessibility while reducing individual crossbar complexity and chip area consumption.
2Area of stationary object
If a large crossbar is split into small crossbars with loop connections, then wiring difficulty and chip area are reduced, but the ID bit width increases with each loop traversal disrupting mutual access between crossbars
Solution Approach 1:
The patent applies ID extension modules at the entry points of loop connections between small crossbars. These modules pre-extend the ID bit width before packets enter the loop, adding the necessary bits to accommodate the cumulative addressing requirements of multiple crossbars. This preliminary action prevents ID overflow and ensures that packets can traverse multiple crossbars without ID bit width mismatches, maintaining mutual access while enabling the segmented architecture.
3Adaptability or versatility
If ID compression is used to adapt ID width to crossbar interface, then ID width matching is achieved, but information loss occurs and bus efficiency decreases due to loss of non-sequential transmission capability
Solution Approach 1:
Instead of compressing the ID to fit the crossbar interface (the conventional approach), the patent inverts the approach by extending the ID bit width to accommodate the larger addressing space required by multiple interconnected crossbars. ID extension modules add bits to the ID rather than removing them, ensuring that each packet retains its unique identifier throughout the looped interconnection structure. This inversion preserves non-sequential transmission capability and bus efficiency while achieving width compatibility across the expanded system.
Data Source
AI summary
A system on chip (soc) and A transmission method under Advanced eXtensible Interface (AXI) bus are disclosed. The system includes a master device, a first extending module, a first interconnection structure, a first subtracting module, a second interconnection structure, and a slave device. The first extending module is configured to add N bits into an identifier (ID) carried in a transmission request, where N is equal to a sum of bits added by all interconnection structures in a longest loop of a system into the ID carried in the transmission request that passes through the interconnection structures. The first subtracting module is configured to subtract M bits from the ID carried in the transmission request output by the first interconnection structure when a slave device to be accessed by the master device is not a slave device connected with the first interconnection structure, where M is equal to the number of bits added by the first interconnection structure into the ID carried in the transmission request that passes through the first interconnection structure. The embodiments reduce costs and avoid the problems caused by ID compression.