AXI Bus Interconnect Apparatus Resolving Deadlocks
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Solution Overview
Problem
The Advanced Microcontroller Bus Architecture (AMBA) bus, particularly the AXI bus, experiences data errors and deadlocks due to its outstanding transaction and out-of-order transmission mechanisms, leading to inaccurate data return and system errors in scenarios with multiple master and slave devices.
Innovation Solution
An interconnect apparatus with a decoder, read instruction ID state recording component, and same-ID sorting buffer component is introduced to manage read instructions by determining the correct routing based on read instruction IDs, preventing data errors and deadlocks through proper sequencing and buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the AXI bus implements outstanding transaction and out-of-order transmission mechanisms to improve transmission speed and system performance, then the transmission efficiency is improved, but data errors and deadlocks occur due to incorrect response sequencing
Solution Approach 1:
The interconnect apparatus performs preliminary actions by recording the IDs of sent read instructions in advance and establishing an expected response sequence. Before processing actual data responses, the system has prepared the sequencing logic, allowing it to correctly associate out-of-order responses with their corresponding requests, thus maintaining data accuracy while enabling high-speed transmission
Solution Approach 2:
The interconnect apparatus acts as an intermediary between master devices and slave devices, introducing ID recording and response sequencing mechanisms. This intermediary component receives read instructions, tracks their IDs, and ensures that responses are correctly matched to requests even when transmitted out of order, thereby resolving the contradiction between speed and accuracy
2Adaptability or versatility
If multiple read instructions with the same ID are transmitted to different slave devices, then the system can handle diverse access requests, but data errors occur due to inability to distinguish response sources
Solution Approach 1:
The system segments the identification of read instructions by combining the basic instruction ID with additional routing information. Even when IDs are the same, the complete identification includes slave device address or port information, allowing the system to distinguish between different slave devices and correctly route responses, thus maintaining both flexibility and accuracy
3Productivity
If the system waits for current transmission to complete before starting next transmission, then data sequencing is simple, but transmission time increases significantly
Solution Approach 1:
The interconnect apparatus implements feedback mechanisms by continuously monitoring transmitted read instruction IDs and comparing received responses against the recorded sequence. This feedback loop enables the system to handle multiple outstanding transactions simultaneously while maintaining correct sequencing, thus achieving high transmission speed without excessive complexity
Data Source
AI summary
The present application discloses an interconnect apparatus for a bus, including at least one decoder, configured to determine, according to at least one read instruction sent by at least one master device, at least one slave device corresponding to the at least one read instruction; a read instruction ID state recording component, Configured to determine the slave device corresponding to the read instruction in response to the decoder, and query, on the basis of a second port of the memory, whether an interconnect apparatus contains a read instruction having the same ID as that of a current read instruction, and configured to route, on the basis of a query result, the current read instruction to a slave device buffer component or a same-ID sorting buffer component corresponding to the read instruction, and write a value into the memory on the basis of a first port of the memory.