AXI4 Augmented Address Logic for FPGA Fabric Reduction

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Solution Overview

Problem

In AXI4 protocol-based systems, instantiating multiple endpoints of the same type leads to increased FPGA fabric use and data propagation delay due to multiple connections required for each instantiation, resulting in reduced design efficiency.

Innovation Solution

The implementation of augmented addressing, where a main entity issues transactions with augmented addresses that include multiple segments, allowing an AXI4 interconnect element to select one of multiple sub entities for transaction execution and a controllable element to select among sub entities with similar functionalities, thereby reducing the need for multiple connections to the interconnect entity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple endpoints of the same type are instantiated in AXI4 protocol-based systems, then system functionality and versatility are improved, but FPGA fabric utilization increases and data propagation delay increases

Engineering Contradiction:
Improvesystem functionalityVSAvoidFPGA fabric utilization
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Multiple endpoints of the same type are merged into a single endpoint instance that can be dynamically configured to handle different functionalities. The controllable element selectively connects the interconnect entity to different sub-entities based on transaction requirements, allowing one physical endpoint to serve multiple logical endpoints, thereby reducing FPGA fabric utilization while maintaining system versatility.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

A single endpoint is designed with multi-functionality to handle multiple different functionalities through dynamic configuration. The controllable element enables this endpoint to universally interface with various sub-entities (DMA controllers, memory interfaces, etc.) by selectively establishing connections based on the transaction type, eliminating the need for multiple dedicated endpoints.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple endpoints of the same type are instantiated in AXI4 protocol-based systems, then system functionality is improved, but data propagation delay increases

Engineering Contradiction:
Improvesystem functionalityVSAvoiddata propagation delay
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

By merging multiple endpoint functions into a single controllable endpoint, the number of separate connection paths through the interconnect entity is reduced. This consolidation shortens the data propagation path and reduces the time required for address decoding and connection establishment, while the controllable element's selective routing maintains the ability to access multiple sub-entities.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If multiple endpoints of the same type are instantiated in AXI4 protocol-based systems, then system functionality is improved, but design efficiency is reduced

Engineering Contradiction:
Improvesystem functionalityVSAvoiddesign efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The design consolidates multiple endpoint instantiations into a single endpoint with dynamic routing capabilities. This reduces the complexity of the AXI4 interconnect configuration, simplifies address decoding logic, and decreases the number of connections that need to be managed, thereby improving design efficiency while maintaining the ability to support multiple functionalities through the controllable element's selective routing.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9965428B2Logic utilization with AXI4 augmented address
Publication Date: 2018.05.08 RAYTHEON CO
  • US9965428B2 patent drawing
  • US9965428B2 patent drawing
  • US9965428B2 patent drawing

AI summary

An advanced extensible interface 4 (AXI4) topology is provided. The topology includes a main entity, parallel sub entities comprising a first sub entity having a first functionality and a second sub entity comprising parallel third sub entities having a second functionality, which is different from the first functionality, and a controllable element in series with the parallel third sub entities and an AXI4 interconnect element serially interposed between the main entity and the parallel sub entities. For a transaction issued by the main entity with an augmented address including first and second addresses, the first address is readable by the AXI4 interconnect element to select one of the first and second sub entities for transaction execution and the second address is readable by the controllable element to select one of the third sub entities for transaction execution.