Axisymmetric Transistor Layout for OLED Pixel Pitch Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Active matrix display devices using organic EL panels face challenges in reducing pixel pitch for high-definition images due to the complex structure of pixel circuits and parasitic capacitance between adjacent data lines, leading to crosstalk and limited lifespan of elements.
Innovation Solution
The solution involves an axisymmetric layout of gate electrodes and impurity diffusion regions for transistors in adjacent pixel circuits, shared integration of gate electrodes, and the use of shielding lines between data lines to reduce parasitic capacitance, allowing for a more efficient arrangement of interconnect layers and minimizing pixel circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If pixel circuits are arranged in a conventional repetitive or mirror pattern, then the layout is simple and manufacturing is easier, but the pixel pitch cannot be reduced sufficiently for high-definition displays
Solution Approach 1:
The patent applies asymmetry by arranging pixel circuits in an asymmetric pattern rather than conventional repetitive or mirror-symmetric layouts. Specifically, the pixel circuits are positioned with different spacing and orientation in different regions of the display panel, allowing for optimized signal routing and reduced parasitic capacitance between adjacent data lines, thereby enabling smaller pixel pitch for high-definition displays.
Solution Approach 2:
The patent utilizes dimensional optimization by arranging pixel circuits in a two-dimensional asymmetric pattern that optimizes both horizontal and vertical spacing. The layout strategically positions pixel circuits to minimize interference in one dimension while maintaining compactness in the other, enabling reduced pixel pitch without increasing overall circuit complexity.
2Length of moving object
If data lines are arranged closely to reduce pixel pitch, then high-definition display is achieved, but parasitic capacitance increases causing crosstalk
Solution Approach 1:
The asymmetric arrangement of pixel circuits creates non-uniform spacing between data lines, which reduces parasitic capacitance coupling. By positioning pixel circuits at asymmetric intervals, the patent ensures that no two adjacent data lines are consistently close over long distances, thereby minimizing cumulative crosstalk while maintaining small pixel pitch.
Solution Approach 2:
The patent introduces shielding structures as intermediary elements between adjacent data lines. These shielding lines, positioned strategically in the asymmetric pixel circuit layout, act as electromagnetic shields that reduce parasitic capacitance coupling and crosstalk between closely spaced data lines, enabling high-definition display without signal interference.
3Duration of action of stationary object
If conventional pixel circuit layouts are used, then manufacturing is simpler, but element lifespan is reduced due to higher current requirements
Solution Approach 1:
The asymmetric pixel circuit layout optimizes current distribution by creating non-uniform spacing between circuits. This arrangement reduces parasitic capacitance that would otherwise require higher drive currents, thereby reducing stress on organic EL elements and extending their operational lifespan while maintaining manufacturability through a systematic layout approach.
Solution Approach 2:
Shielding structures serve as intermediary elements that reduce electromagnetic interference and parasitic capacitance between adjacent pixel circuits. By minimizing these harmful effects, the patent reduces the current levels required for stable operation, thereby extending element lifespan without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a reduced pixel pitch for high-definition displays while minimizing crosstalk and extending the lifespan of elements by optimizing the layout and integration of transistors and data lines.
Implementation Method 1
An organic EL panel is configured by arranging organic light emitting diodes (Organic Light-Emitting Diode: OLED) having a light emitting layer made of an organic compound... Such an organic light emitting diode emits light when molecules of the organic compound, which have been excited by energy, generated by recombination of electrons and holes that are injected into the light emitting layer, return from the excited state to the ground state.
Data Source
AI summary
Provided is an active matrix display device using an organic EL panel including: a plurality of pixel circuits each including an organic light emitting diode arranged in a pixel region of the organic EL panel and a plurality of transistors configured to drive the organic light emitting diode; a plurality of scanning lines arranged along a first direction in the organic EL panel; and a plurality of data lines arranged along a second direction that is orthogonal to the first direction. In at least one set of pixel circuits that are adjacent in the first direction, gate electrodes and impurity diffusion regions of the plurality of transistors have an axisymmetric layout. Gate electrodes of at least one set of transistors that are symmetrically arranged in the at least one set of pixel circuits are integrated.