B-TRAN Turn-Off Circuit for Fast Inductive Load Shutoff
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Solution Overview
Problem
Bi-directional double-base bipolar junction transistors (B-TRANs) face challenges in reducing breakdown voltage differences between collector-emitters and achieving fast shutoff times, especially under inductive loads, due to the Beta effect and limitations in existing transistor turn-off methods.
Innovation Solution
The method involves using upper-main and lower-main switches with FETs to interrupt and commutate load currents through the B-TRAN, employing diode turn-off techniques to quickly reverse bias PN junctions and block current flow, and optionally using pre-turn-off modes to further reduce transition times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional transistor turn-off methods are used, then the transistor can block current, but the shutoff time is slow especially under inductive loads
Solution Approach 1:
The patent applies preliminary action by using a first shutoff current to pre-bias the PN junction before the main turn-off event. This preliminary current prepares the junction by creating an initial reverse bias condition, which accelerates the subsequent turn-off process and reduces storage time, especially under inductive loads where traditional methods struggle.
Solution Approach 2:
The patent introduces an intermediary mechanism by using a dedicated shutoff current path and control circuitry that mediates between the main load current and the turn-off process. This intermediary system allows independent control of the turn-off current, enabling faster extraction of stored charge without compromising the main current blocking capability.
2Power
If the Beta effect is present in B-TRAN, then current amplification is achieved, but breakdown voltage differences between collector-emitters increase
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bias conditions and current distribution in the B-TRAN during operation. By changing the operating parameters (current levels, voltage distribution) and using active control circuits, the system compensates for the Beta effect's impact on breakdown voltage differences, maintaining more uniform breakdown characteristics while preserving current amplification.
3Loss of time
If fast shutoff is achieved under inductive loads, then transition time is reduced, but voltage spikes and oscillations increase
Solution Approach 1:
The patent applies beforehand cushioning by incorporating snubber circuits and damping elements that are pre-configured to absorb and dissipate voltage spikes and oscillations generated during fast turn-off of inductive loads. This cushioning mechanism is in place before the switching event, ready to mitigate the harmful effects of rapid transitions.
Solution Approach 2:
The patent converts the harmful voltage spikes generated by fast switching into beneficial diagnostic information and controlled energy dissipation. By using controlled avalanche breakdown and clamping circuits, the energy that would otherwise be destructive is channeled through defined paths, protecting the transistor while maintaining fast switching performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces breakdown voltage and shutoff time, enhances current blocking capabilities, and improves performance under inductive loads, achieving faster transitions to non-conductive states compared to traditional transistor turn-off methods.
Implementation Method 1
interrupting the first load current from the lower collector-emitter to the lower terminal by opening a lower-main FET
Implementation Method 2
commutating a first shutoff current through a lower base of the transistor to the lower terminal; blocking current from the upper terminal to the lower terminal by the transistor
Data Source
AI summary
Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper-main lead of the transistor, through the transistor, and from a lower-main lead of the transistor to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower-main lead to the lower terminal by opening a lower-main FET and commutating a first shutoff current through a lower-control lead the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.


