Back-Bias DAC Circuit for Beyond-Rail SOI Gate Biasing
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Solution Overview
Problem
Conventional back bias generator circuits are limited in generating output voltages beyond the supply rails, restricting the range of back-gate bias voltages for SOI MOS transistors, which hinders performance optimization in terms of speed and leakage.
Innovation Solution
A non-adaptive open loop back bias generator circuit with a special purpose digital to analog converter (DAC) and switched capacitor circuits, capable of generating bipolar output voltages exceeding the supply voltage range, utilizing a resistor string and switching network to produce extended voltage ranges without requiring additional components or area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional bulk planar MOS architecture is used, then the structure is simple and manufacturing is easier, but the back-gate voltage range is limited by junction diodes between source/drain and well
Solution Approach 1:
The patent segments the well structure into separate P-well and N-well regions that can be independently biased. This segmentation allows each well to be controlled with different voltage ranges, overcoming the limitation of the conventional single well structure where the back-gate voltage range is constrained by the junction diodes between source/drain and the well.
2Adaptability or versatility
If the back-gate voltage range is extended beyond supply rails, then performance optimization in terms of speed and leakage is improved, but conventional circuits cannot generate voltages beyond supply rails
Solution Approach 1:
The patent introduces an intermediary charge pump circuit that generates voltages beyond the supply rails (above VDD and below VSS). This intermediary voltage generation mechanism enables the back-gate biasing circuit to achieve extended voltage ranges without directly modifying the core DAC or control logic, thus managing complexity through modular addition.
Solution Approach 2:
The patent changes the operating parameters of the circuit by introducing switched capacitor circuits that can operate with control signals beyond the standard supply rails. The DAC is modified to accept control signals with voltages above VDD and below VSS, enabling it to generate back-gate bias voltages that extend beyond the conventional supply voltage range, thereby optimizing transistor performance in terms of speed and leakage.
3Adaptability or versatility
If separate deep N-well is used for each device with higher P-well voltage, then the back-gate voltage range is extended, but the area increases
Solution Approach 1:
The patent implements a universal back-gate biasing circuit that can serve multiple devices with different P-well voltage requirements. Instead of creating separate deep N-well structures for each device, the circuit uses independent P-well and N-well control mechanisms that can be shared across multiple devices, thereby extending the back-gate voltage range without proportionally increasing the chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables area-efficient generation of bipolar output voltages beyond the conventional supply limits, allowing for improved control of back-gate bias voltages for SOI MOS transistors, enhancing performance and flexibility in power consumption and speed trade-offs.
Implementation Method 1
an upper and a lower switched capacitor circuit... The upper switched capacitor circuit and the lower switched capacitor circuit are designed to generate and supply an extended upper voltage to the upper input terminal of the DAC and an extended lower voltage to the lower input terminal of the DAC
Implementation Method 2
the DAC is formed of a resistor string and a switching network... the resistor string being connected between the upper supply terminal and the lower supply terminal
Data Source
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AI summary
The present invention relates to a back bias generator circuit having a special DAC for generating an output voltage (OUT) on a digital input to the circuit, an upper and a lower switched capacitor circuit, and a control unit. The DAC is formed of a resistor string and a switching network of several switching transistors. A voltage difference at an uppermost resistor of the resistor string and at a lowermost resistor of the resistor string, respectively, is used in the corresponding switched capacitor circuits to generate an extended upper voltage (VDDH) and an extended lower voltage (VSSL) which may be passed via the switching network to the output of the DAC. The proposed back bias generator circuit is able to generate an output voltage exceeding the upper and lower limits of the supply voltage and allows an area efficient implementation.