Back-Bias Delay Matching in Semiconductor Self-Refresh Circuits
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining stable self-refresh operations during power-down modes due to mismatched delay times between bank selection signals and addresses, which are affected by variations in back-bias voltage levels.
Innovation Solution
Incorporating a delay time adjustment circuit that adjusts the supply of charges to internal nodes based on back-bias voltage levels, and an address input circuit that delays addresses in response to bank selection signals, ensuring synchronized operation by varying delay times according to voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay times are fixed in power-down mode, then circuit operation is simple, but self-refresh operation becomes unstable due to mismatched delay times between bank selection signals and addresses
Solution Approach 1:
The patent implements dynamic delay time adjustment by controlling the charging speed of internal nodes through back-bias voltage. The delay time adjustment circuit varies the delay time of bank selection signals based on back-bias voltage levels, allowing the system to adapt delay characteristics to different operating conditions rather than using fixed delay circuits
Solution Approach 2:
The patent changes the voltage parameter (back-bias voltage level) to control the delay time characteristic. By adjusting the back-bias voltage applied to transistors in the delay circuit, the charging speed of internal nodes changes, which directly modifies the delay time of bank selection signals to match address signal delays
2Adaptability or versatility
If back-bias voltage level increases, then delay time adjustment range increases, but charging speed of internal nodes decreases causing longer delay times
Solution Approach 1:
The patent utilizes back-bias voltage as a controllable parameter to adjust delay time. By varying the back-bias voltage level, the transistor threshold voltage changes, which controls the charging speed of internal nodes and thereby adjusts the delay time to match different operating conditions
3Reliability
If delay times are not matched, then circuit operation is simple, but undesired word line activations occur during self-refresh
Solution Approach 1:
The patent employs feedback control where the delay time adjustment circuit monitors the back-bias voltage level and automatically adjusts the delay time of bank selection signals accordingly. This closed-loop approach ensures that delay times remain matched under varying voltage conditions without requiring complex external calibration
Data Source
AI summary
A semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.