Back Bias ESD Protection Circuit for Ultra-Low Power Leakage
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Solution Overview
Problem
In ultra-low power applications, static leakage from ESD devices is significant, and existing ESD protection circuits result in substantial current leakage, which degrades IC performance, and incorporating a switch to activate ESD devices doubles the circuit size and cost.
Innovation Solution
The implementation of a back bias signal to ESD protection semiconductor switches, using a bias circuit to reduce static leakage current by applying a negative or positive voltage to isolated wells of BigFETs, thereby reducing static current draw by up to 20 times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection circuits are implemented in ultra-low power applications, then device protection is improved, but static leakage current increases significantly
Solution Approach 1:
The patent applies reverse body bias (RBB) dynamically to the ESD clamp transistor P1. During normal operation, RBB is continuously applied to minimize leakage current. During ESD events, the bias is adjusted to ensure proper protection function. This dynamic biasing approach allows the circuit to adapt its characteristics based on operational conditions, resolving the contradiction between protection reliability and energy loss.
Solution Approach 2:
The patent changes the electrical parameters of the ESD clamp transistor by applying reverse body bias voltage to the n-well. This parameter change (applying negative voltage to the well) directly reduces the off-state leakage current of the transistor while maintaining its protection function. The high-voltage supply Vccbi applies RBB to the clamp transistor P1, changing its electrical characteristics to reduce static leakage.
2Loss of energy
If switches are added to activate ESD devices selectively, then static leakage is reduced, but circuit size and cost double
Solution Approach 1:
The patent makes the existing control transistors (N1 and N2) serve multiple functions. Transistor N1 not only controls the timing of RBB application but also connects the n-well to Vcc during ESD events. Transistor N2 serves both as a pull-up device and as part of the RBB application mechanism. This multi-functionality eliminates the need for additional switches, reducing circuit complexity while maintaining leakage reduction benefits.
Solution Approach 2:
The patent merges the RBB application circuitry with the existing ESD protection circuit structure. The inverter and RC timer that already exist in the circuit are utilized to control the timing of RBB application. The control transistors N1 and N2 are integrated into the existing circuit topology, combining multiple functions into a unified structure that reduces overall circuit size while achieving selective ESD activation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces static leakage current in ESD protection circuits, from 300µA to 15µA in ICs with 100 ESD protection circuits, enhancing the power efficiency of ultra-low power ICs without increasing circuit size or cost.
Implementation Method 1
a bias circuit configured to provide a back bias signal to an isolated well of the ESD protection semiconductor switch when IO circuit is in normal operation
Data Source
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AI summary
An input/output (IO) circuit including: an IO driver circuit; an electrostatic discharge (ESD) protection semiconductor switch with a first input configured to receive an ESD, a second input connected to an ESD rail, and a switch control input; an ESD trigger circuit connected to the switch control input, wherein the ESD trigger circuit is configured to produce a trigger signal to close the protection semiconductor switch when the ESD detection circuit detects an ESD; and a bias circuit configured to provide a back bias signal to an isolated well of the ESD protection semiconductor switch when IO circuit is in normal operation.