Floating-Body Memory Cell Using Back Bias for Refresh-Free Storage
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Solution Overview
Problem
Conventional semiconductor memory devices, particularly those using floating body transistors, face challenges in achieving multiple stable states without the need for periodic refresh operations, which limits their scalability and efficiency in data storage.
Innovation Solution
A semiconductor memory cell design featuring a floating body region bounded by insulating regions and a buried layer, where a back bias is applied to create a depletion region, allowing for the injection or extraction of charge to maintain the memory cell state, enabling two stable charge levels without the need for refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floating body transistor memory is used, then the memory can store data, but it requires periodic refresh operations which reduces productivity
Solution Approach 1:
The memory cell uses the floating body region to automatically maintain its charge state through impact ionization and charge accumulation effects. The floating body acts as a self-regulating charge storage mechanism that maintains stable states without external refresh operations, allowing the memory to serve itself rather than requiring periodic intervention
Solution Approach 2:
The invention changes the electrical parameters of the transistor by creating a floating body region with controlled charge accumulation. By modifying the body charge state through impact ionization during write operations, the memory achieves bi-stability with distinct high and low states that can be maintained indefinitely without refresh, fundamentally altering the electrical behavior from conventional transistors
2Device complexity
If conventional 1T/1C memory cell is used, then the memory cell has simple structure, but it requires capacitor which increases device complexity when scaling
Solution Approach 1:
The invention extracts and removes the capacitor component from the conventional 1T/1C memory cell structure. By eliminating the capacitor and using only a single transistor with a floating body region to store charge, the design simplifies the memory cell structure while maintaining charge storage functionality through the floating body's charge accumulation mechanism
Solution Approach 2:
The floating body region serves multiple functions: it acts as the charge storage element replacing the capacitor, provides gain through impact ionization, and enables bi-stable operation. This multi-functional design eliminates the need for separate capacitor and transistor components, achieving universal functionality in a single transistor structure
3Reliability
If floating body region is not properly isolated, then manufacturing is simpler, but charge leakage occurs reducing reliability
Solution Approach 1:
The buried insulating layer acts as an intermediary element that electrically isolates the floating body region from the substrate. This intermediate layer prevents charge leakage paths while maintaining the floating body's electrical floating state, serving as a mediator between the floating body and the substrate without requiring complex isolation structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for efficient data storage with reduced operational voltages and simplified circuitry, enhancing the scalability and reliability of semiconductor memory devices by eliminating the requirement for periodic refresh operations.
Implementation Method 1
DRAM based on the electrically floating body effect has been proposed
Implementation Method 2
a depletion region formed as a result of an application of a back bias to the buried layer region
Data Source
AI summary
A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.