Back Bias Regulator Circuit for Dynamic Threshold Control

Solution Overview

Problem

In integrated circuits with Sea-of-Gates, uncontrolled transitions of back bias levels can lead to timing violations and logic malfunctions, necessitating a regulator circuit that adjusts threshold voltages of PMOS and NMOS transistors without stopping logic activity.

Innovation Solution

A back bias regulator circuit that controls the transition of back bias voltages by setting N well and P well potentials in a correlated manner using amplifiers and resistors, ensuring well-controlled and timely adjustments without interrupting the clock, and utilizing charge pumps to maintain circuit stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If back bias levels are dynamically controlled to adjust threshold voltages, then power consumption can be reduced or performance enhanced, but timing violations may occur if transitions are not well controlled

Engineering Contradiction:

Improvepower consumptionVSAvoidtiming violations

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The circuit performs preliminary actions by pre-charging and pre-discharging capacitive loads through controlled current paths before actual back bias transitions. The regulator circuit prepares the back bias voltage levels in advance using charge pumps and controlled switching, ensuring that transitions occur smoothly without sudden jumps that would cause timing violations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The regulator circuit implements feedback control to monitor and adjust back bias voltage transitions. The circuit uses feedback signals to control the switching of transistors that regulate back bias voltage application to PMOS and NMOS devices, ensuring that threshold voltage adjustments occur within timing constraints while achieving power consumption reduction.

Inventive Principle:

Principle #23Feedback

2Speed

If back bias levels are dynamically controlled to adjust threshold voltages, then performance can be enhanced, but timing violations may occur if transitions are not well controlled

Engineering Contradiction:

ImproveperformanceVSAvoidtiming violations

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The circuit performs preliminary actions by pre-charging and pre-discharging capacitive loads through controlled current paths before actual back bias transitions. The regulator circuit prepares the back bias voltage levels in advance using charge pumps and controlled switching, ensuring that transitions occur smoothly without sudden jumps that would cause timing violations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The regulator circuit implements feedback control to monitor and adjust back bias voltage transitions. The circuit uses feedback signals to control the switching of transistors that regulate back bias voltage application to PMOS and NMOS devices, ensuring that threshold voltage adjustments occur within timing constraints while achieving performance enhancement.

Inventive Principle:

Principle #23Feedback

3Use of energy by moving object

If threshold voltages are adjusted dynamically, then power consumption can be optimized, but logic activity must be stopped which causes time overhead

Engineering Contradiction:

Improvepower consumptionVSAvoidtime overhead

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The regulator circuit enables continuous adjustment of back bias voltages during active logic operation without requiring system shutdown or clock stopping. The circuit uses continuously operating charge pumps and feedback-controlled switching mechanisms that maintain logic activity while dynamically optimizing threshold voltages for power consumption reduction.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The circuit performs preliminary actions by pre-charging and pre-discharging capacitive loads through controlled current paths before actual back bias transitions. The regulator circuit prepares the back bias voltage levels in advance using charge pumps and controlled switching, ensuring that transitions occur smoothly without sudden jumps that would cause timing violations.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10394264B1Back bias regulator circuit and method therefor

Publication Date: 2019.08.27 NXP USA INC

AI summary

A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.