Back-Biased MOSFET Amplifier for Low-Power Sensor Buffering
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Solution Overview
Problem
Capacitive sensors, such as audio microphones and pressure sensors, face challenges in amplifying and buffering signals effectively due to high output impedance and electrical noise, especially in low-power applications where power for amplifying and buffering circuitry is limited.
Innovation Solution
The amplifier design includes a bias circuit, open-loop gain stage, and buffer stage with specific configurations of MOSFETs and resistors, utilizing back bias generation and large impedance circuits to minimize current draw while providing low-impedance output, and incorporates capacitors using analog floating gate technology to mitigate noise and common-mode voltage issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional amplification and buffering circuitry is used for capacitive sensors, then signal amplification and buffering are achieved, but power consumption increases and electrical noise is introduced
Solution Approach 1:
The amplifier employs a periodic switching scheme where the capacitive sensor is connected to either the input or output of the amplifier in alternating phases. During the first phase, the sensor charges a sampling capacitor through the input. During the second phase, the stored charge is transferred to the output through the buffer. This periodic operation allows the amplifier to function with minimal continuous power consumption, as the switching elements (MOSFETs) only conduct during specific phases rather than continuously, thereby resolving the contradiction between achieving signal amplification/buffering and minimizing power consumption.
2Power
If high output impedance capacitive sensors are directly amplified, then signal amplification is achieved, but electrical noise and signal integrity deteriorate
Solution Approach 1:
The amplifier introduces a sampling capacitor as an intermediary element between the high-impedance capacitive sensor and the amplification stage. The sensor charges this intermediate capacitor during the input phase, isolating the sensor from the noisy amplification circuitry. The sampled voltage on this intermediate capacitor is then transferred to the output during the buffer phase. This intermediary capacitor acts as a buffer that prevents direct interaction between the high-impedance sensor and the noisy amplifier, thereby reducing electrical noise and maintaining signal integrity while still achieving signal amplification.
3Use of energy by moving object
If low-power amplifier circuitry is used, then power consumption is reduced, but amplification capability and buffering performance are compromised
Solution Approach 1:
The amplifier employs dynamic switching of MOSFETs to control the flow of current and charge between the input, output, and sampling capacitor. During the input phase, specific MOSFETs are turned on to charge the sampling capacitor from the sensor. During the buffer phase, different MOSFETs are activated to transfer the charge to the output. This dynamic switching allows the amplifier to achieve full amplification capability during active phases while consuming minimal power during transition and idle periods, effectively resolving the contradiction between low power consumption and adequate amplification capability.
Data Source
AI summary
In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.