Back-Biased SOI Transistors With Embedded DRAM On Intrinsic Layer
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Solution Overview
Problem
The integration of back-biased planar fully or partially depleted SOI transistors with embedded DRAMs is challenging due to the need for electrical insulation of back-biasing regions, which is hindered by the presence of a thick pre-doped n+ layer, leading to potential defects and doping of the SOI layer during high implantation doses.
Innovation Solution
A method involving the formation of a wafer with a doped layer, an intrinsic semiconductor layer, and a buried oxide layer, allowing for the separate creation of back-biased transistors and embedded DRAMs without requiring complex processing for back-biasing regions, by doping the intrinsic semiconductor layer with n or p dopants, enabling control of threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick pre-doped n+ layer is used to contain the DRAM capacitor trench, then the DRAM capacitor can be properly formed, but high implantation doses are required which create defects and dope the SOI layer
Solution Approach 1:
The patent segments the doped layer into two distinct parts: a thick pre-doped n+ layer (several microns thick) that serves as the capacitor back plate and containment structure, and a thinner intrinsic or lightly-doped first semiconductor layer (10-300 nm) that serves as the back-biasing region for SOI transistors. This segmentation allows the thick doped layer to provide adequate capacitor support while the thinner intrinsic layer enables low-dose implantation for back-biasing without creating defects or unwanted doping.
Solution Approach 2:
The patent applies local quality by having different doping characteristics in different regions of the doped layer. The capacitor region has high doping concentration (n+) for proper capacitor formation, while the back-biasing region has intrinsic or light doping to enable controlled low-dose implantation. This local differentiation resolves the contradiction by allowing high doping where needed for capacitor support and low doping where needed for defect-free back-biasing.
2Adaptability or versatility
If high implantation doses are used to create back-biasing regions in the presence of a thick pre-doped n+ layer, then back-biasing can be achieved, but defects are created and the SOI layer becomes doped
Solution Approach 1:
The patent segments the semiconductor structure into distinct layers with different doping levels, placing the back-biasing implantation target in the intrinsic or lightly-doped first semiconductor layer rather than in the thick pre-doped n+ layer. This segmentation enables low-dose implantation to achieve back-biasing capability while avoiding the creation of defects and unwanted doping that would occur with high-dose implantation into the heavily doped n+ layer.
3Reliability
If a thick pre-doped n+ layer is used for eDRAM, then capacitor containment is achieved, but complex processing is required for preparation of back-biasing regions
Solution Approach 1:
The patent segments the wafer structure into distinct functional regions: the thick pre-doped n+ layer for capacitor containment and the thinner intrinsic first semiconductor layer for back-biasing. This segmentation simplifies processing because the back-biasing regions can be formed by direct implantation into the intrinsic layer without requiring complex preparation steps to modify the thick n+ layer, thereby reducing overall device complexity while maintaining reliable capacitor containment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates the manufacture of integrated embedded DRAMs and back-biased SOI transistors with reduced risk of defects, allowing for dynamic adjustment of threshold voltage and efficient back-biasing without the need for high implantation doses.
Implementation Method 1
forming a back-biasing region in the intrinsic first semiconductor layer by doping at least a part of the intrinsic first semiconductor layer of the already provided wafer with n or p dopants
Implementation Method 2
providing a buried oxide layer on the intrinsic first semiconductor layer
Implementation Method 3
growing a doped layer on a semiconductor substrate; growing an intrinsic first semiconductor layer on the doped layer
Data Source
Figure 1
Figure 2A~2B
AI summary
The present invention relates to a method for the manufacture of a wafer, comprising the steps of providing a doped layer (6) on a semiconductor substrate (5); providing a first intrinsic semiconductor layer (7) on the doped layer; providing a buried oxide layer (9) on the first semiconductor layer; and providing a second semiconductor layer (3) on the buried oxide layer. In a first region (A) of the wafer, DRAM devices are formed with capacitor trenches (10) extruding into the doped layer (6). In a second region (B) of the wafer, logic TFTs (13) are formed. The first semiconductor layer (7) is doped at locations below the TFTs. These doped regions are provided with contacts (14) for back-biasing the TFTs.