Back-Channel FET Pull-Back Structure to Prevent Channel Damage
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Solution Overview
Problem
The fabrication of back channel Field Effect Transistors (FETs) is complex due to the need for chemical mechanical polish (CMP) and trench etch processes, which can damage the semiconductor channel material and result in electrical shorts, whereas front channel FETs face damage during dielectric layer deposition.
Innovation Solution
A pull back process using an etch-stop layer to prevent electrical connections between gate electrodes and source/drain electrodes, simplifying the fabrication of back channel FETs by depositing the semiconductor layer after the gate dielectric, and employing a high-k dielectric layer and etch-stop layers to prevent damage and shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If CMP and trench etch processes are used to fabricate back channel FETs, then the gate electrode can be formed below the dielectric layer, but the semiconductor channel material is damaged and electrical shorts occur
Solution Approach 1:
The patent inverts the conventional fabrication sequence by forming the gate electrode first, then depositing the dielectric layer, and finally forming the semiconductor channel layer on top. This reverse approach avoids exposing the semiconductor channel to damaging CMP and trench etch processes while still achieving the back channel FET structure where the gate is below the dielectric layer.
Solution Approach 2:
The gate electrode is formed in advance before the dielectric layer and semiconductor channel layer are deposited. This preliminary formation of the gate electrode allows subsequent layers to be deposited without requiring damaging removal processes, preventing semiconductor channel damage while establishing the back channel configuration.
2Ease of operation
If dielectric layer is deposited over semiconductor channel layer in front channel FETs, then the gate electrode can apply voltage to create a channel, but the semiconductor channel material is damaged during deposition
Solution Approach 1:
The patent inverts the layer deposition sequence by forming the dielectric layer before the semiconductor channel layer. This reversal prevents the semiconductor channel from being exposed to harmful deposition conditions while still allowing the gate electrode to apply voltage effectively to create the conductive channel when needed.
3Device complexity
If traditional back channel FET fabrication processes are used, then the gate electrode is formed below the dielectric layer, but the process is complex and time-consuming
Solution Approach 1:
The gate electrode is formed in advance before subsequent layers are deposited, eliminating the need for time-consuming CMP and trench etch processes that would otherwise be required to create the back channel structure. This preliminary formation significantly reduces fabrication time while maintaining the complex back channel architecture.
Solution Approach 2:
The patent extracts and removes the harmful CMP and trench etch processes from the fabrication sequence, keeping only the essential steps needed to form the back channel FET structure. This extraction of unnecessary complex steps simplifies the overall process and reduces manufacturing time.
Data Source
AI summary
A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.