Back Channel FET Pull-Back Structure to Prevent Gate Shorts
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Solution Overview
Problem
The fabrication of back channel Field Effect Transistors (FETs) is complex due to the need for chemical mechanical polish (CMP) and trench etch processes, which can damage the semiconductor channel material and result in electrical shorts, whereas front channel FETs face damage during dielectric layer deposition.
Innovation Solution
A pull back process using an etch-stop layer to prevent electrical connections between gate electrodes and source/drain electrodes, simplifying the fabrication of back channel FETs by depositing the semiconductor layer after the gate dielectric, and employing a high-k dielectric layer and etch-stop layers to prevent damage and shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If CMP and trench etch processes are used to fabricate back channel FETs, then the gate electrode can be formed below the dielectric layer, but the semiconductor channel material is damaged and electrical shorts occur
Solution Approach 1:
The patent inverts the conventional FET structure by placing the gate electrode below the dielectric layer instead of above it. This inversion allows the gate to be formed before the semiconductor channel material is deposited, eliminating the need for damaging CMP and trench etch processes that would otherwise be required to create cavities for the gate electrode.
Solution Approach 2:
The gate electrode is formed preliminarily before the semiconductor channel material is deposited. This preliminary action allows the gate structure to be established first, then the semiconductor material is deposited over it without requiring subsequent etching or polishing to create the gate cavity, thus preventing damage to the channel material.
2Device complexity
If the gate electrode is formed below the dielectric layer in back channel FETs, then a back channel structure is achieved, but complex CMP and trench etch processes are required
Solution Approach 1:
By inverting the gate position to below the dielectric layer, the patent enables a simplified fabrication sequence where the gate is formed first, followed by dielectric deposition, then semiconductor material deposition. This eliminates the need for complex CMP and trench etch processes that would be required to create cavities for a conventional gate structure.
Solution Approach 2:
The gate electrode is formed as a preliminary structure before subsequent layers are deposited. This preliminary formation of the gate allows the dielectric and semiconductor layers to be deposited conformally over it, eliminating the need for complex post-deposition processing such as CMP and trench etching.
3Ease of manufacture
If conventional FET fabrication processes are used, then dielectric layers can be deposited, but the semiconductor channel material is damaged during deposition
Solution Approach 1:
The gate electrode is formed preliminarily before the dielectric layer is deposited. This allows the dielectric to be deposited conformally over the gate structure without requiring subsequent etching to create cavities, thereby avoiding damage to the semiconductor channel material that would occur during such etching processes.
Solution Approach 2:
By inverting the gate position to below the dielectric layer, the patent enables the dielectric to be deposited directly over the gate without requiring cavity formation. This inversion of the conventional structure allows damage-free deposition of the dielectric layer followed by conformal deposition of the semiconductor channel material.
Data Source
AI summary
A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.