Back Source/Drain Contact Geometry for Low-Capacitance Semiconductors
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Solution Overview
Problem
As semiconductor devices scale down, there is a need to reduce parasitic capacitance and ensure electrical stability between contacts to improve device performance and reliability.
Innovation Solution
The semiconductor device incorporates a back interlayer insulating film with back wiring lines, source/drain patterns, and back source/drain contacts featuring convex and concave shapes or saddle structures to enhance electrical connectivity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch size of semiconductor devices is decreased to increase device density, then device density is improved, but parasitic capacitance increases and electrical stability between contacts deteriorates
Solution Approach 1:
The patent transitions from conventional planar contacts to three-dimensional contacts with convex and concave structures. The back source/drain contact includes a convex portion that protrudes toward the source/drain pattern and a concave portion that recesses, creating vertical dimensionality that reduces overlap area with wiring lines while maintaining electrical connection, thereby reducing parasitic capacitance in high-density configurations
Solution Approach 2:
The contact structure features non-uniform geometry with distinct convex and concave regions. The convex portion optimizes electrical connection to the source/drain pattern, while the concave portion reduces capacitance coupling to the back wiring line. This localized differentiation of contact geometry allows simultaneous optimization of electrical stability and parasitic capacitance reduction
2Ease of manufacture
If conventional planar contacts are used in high-density devices, then manufacturing is simpler, but parasitic capacitance increases and electrical stability deteriorates
Solution Approach 1:
The contact structure incorporates curved surfaces including convex portions that protrude and concave portions that recess, rather than flat planar geometries. These curved features are formed through standard semiconductor processing techniques such as anisotropic etching, allowing the complex three-dimensional shape to be manufactured using conventional fabrication workflows while achieving reduced parasitic capacitance and improved electrical stability
Data Source
AI summary
A semiconductor device includes a back interlayer insulating film, a back wiring line within the back interlayer insulating film, a first source/drain pattern on the back wiring line, a second source/drain pattern on the back wiring line and spaced apart from the first source/drain pattern, and a back source/drain contact between the first source/drain pattern and the back wiring line, connected to the first source/drain pattern, and overlapping with the first source/drain pattern. The back source/drain contact is connected to the first source/drain pattern and, in a cross-sectional view cut perpendicular to a third direction, a first surface of the back source/drain contact has a convex shape, and in a cross-sectional view cut perpendicular to a second direction, the first surface of the back source/drain contact has a concave shape.