Back Control Gate Transistors for Lithography Resolution Limits
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Solution Overview
Problem
Current semiconductor processing technologies face challenges in achieving precise control over transistor channel widths due to lithography resolution limits, leading to uniformity issues and reduced flexibility in designing electronic circuits, as well as inefficiencies in wafer space utilization and isolation methods.
Innovation Solution
The introduction of a semiconductor device structure on a SeOI substrate with a back control gate region that allows for adjustable biasing to simulate modifications in channel width, enabling dynamic control of transistor threshold voltage and effective channel width, thereby overcoming the limitations of traditional lithography and isolation techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lithography is used to define transistor channel widths, then manufacturing process is simplified, but manufacturing precision deteriorates due to resolution limits
Solution Approach 1:
The channel width control is segmented into two independent components: the physical lithographic pattern and the electrical back-gate voltage control. This allows the lithography step to define only the active zone boundaries while the effective channel width is independently adjusted via back-gate biasing, resolving the contradiction between lithographic simplicity and width precision.
Solution Approach 2:
The invention changes the control parameter for channel width from purely geometric (lithographic dimension) to electrical (back-gate voltage). By applying different voltages to the back-gate, the effective channel width can be continuously modulated without requiring different lithographic patterns, thus maintaining manufacturing precision while simplifying the fabrication process.
2Adaptability or versatility
If different channel widths are fabricated using lithography, then circuit design flexibility is improved, but manufacturing precision deteriorates due to variability in pattern transfer
Solution Approach 1:
The invention separates the channel width definition into a uniform lithographic active zone pattern and a variable electrical back-gate control. This segmentation allows all transistors to be fabricated with identical lithographic patterns (ensuring manufacturing precision) while achieving different effective channel widths through electrical tuning (providing design flexibility).
Solution Approach 2:
The invention introduces dynamic electrical control of channel width via back-gate voltage, transforming the static geometric width defined by lithography into a dynamically adjustable parameter. This allows circuit design flexibility to be achieved through voltage control rather than through variable lithographic patterns, thereby eliminating pattern transfer variability.
3Manufacturing precision
If long strips of transistors with identical dimensions are used, then manufacturing precision is improved, but adaptability deteriorates due to loss of geometric width variation
Solution Approach 1:
The invention transforms the static uniform geometric width into a dynamically controllable effective width through back-gate voltage. All transistors can be manufactured with identical dimensions (improving precision) while the back-gate voltage provides dynamic adjustment of the effective channel width (restoring adaptability).
Solution Approach 2:
The invention changes the controlling parameter for channel width from geometric dimension to electrical voltage. This allows uniform lithographic patterns to produce transistors with different effective widths through voltage modulation, simultaneously achieving manufacturing precision and design adaptability.
4Reliability
If shallow trench isolation is used for transistor isolation, then device performance is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The invention extracts the isolation function from the complex shallow trench isolation structure and implements it through electrical control of the back-gate. By applying appropriate voltages to the back-gate, the channel can be fully depleted, providing effective electrical isolation without requiring physical trench structures, thereby reducing device complexity while maintaining isolation performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a wide range of performance modulation in transistors with a single physical channel width, reducing leakage currents and simplifying design rules, while enabling more efficient use of wafer space and flexible circuit design.
Implementation Method 1
a back control gate region formed in the base substrate beneath the channel region. This back gate region is capable of being biased in order to shift the threshold voltage of the transistor
Data Source
AI summary
This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.