Back End Floating Gate Structure for Non-Volatile Memory
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices rely on volatile memory cells, which lose data when power is removed, limiting their ability for long-term storage and caching in semiconductor devices, and existing solutions do not efficiently integrate non-volatile memory structures in the back end region without increasing complexity and cost.
Innovation Solution
Incorporating a non-volatile memory cell structure with a floating gate structure in the back end region of semiconductor devices, where a portion of the dielectric layer is between the gate and word line conductive structures, allowing charge storage even without power, and using similar processing techniques as DRAM cells to minimize additional masking steps and processing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If volatile memory cells are used in DRAM devices, then the device can achieve lower cost and smaller area, but data is lost when power is removed, limiting long-term storage capability
Solution Approach 1:
The patent combines volatile and non-volatile memory cell structures into a single hybrid memory cell, where the capacitor structure provides volatile storage and the floating gate structure provides non-volatile storage. This merging allows data retention without power while maintaining the cost and area benefits of DRAM architecture.
Solution Approach 2:
The hybrid memory cell structure serves multiple functions: it can operate as volatile memory when powered, as non-volatile memory when unpowered, and provides both caching and long-term storage capabilities within the same device, eliminating the need for separate memory types.
2Adaptability or versatility
If non-volatile memory structures are integrated in the back end region, then caching and long-term storage are enabled, but processing complexity and cost increase due to additional masking steps
Solution Approach 1:
The patent merges the formation of volatile and non-volatile memory structures into a single integrated process flow. The same dielectric layers, conductive structures, and patterning steps are used to create both capacitor and floating gate components simultaneously, eliminating the need for separate masking steps for each memory type.
Solution Approach 2:
The processing techniques used for DRAM cell fabrication are made universal to also create non-volatile memory structures. The same deposition, etching, and patterning processes form both the capacitor structure and the floating gate structure, allowing existing manufacturing lines to produce hybrid memory without additional complexity.
3Reliability
If a dielectric layer is placed between the gate and word line conductive structures to form a floating gate structure, then charge storage is enabled without power, but the device structure becomes more complex
Solution Approach 1:
The patent extracts a portion of the dielectric layer to create a recess that houses the floating gate structure. This extraction creates the necessary physical separation between the word line and the gate structure, enabling charge storage while using the same dielectric material already present in the DRAM architecture.
Solution Approach 2:
The floating gate structure is nested within the existing DRAM cell structure. The dielectric layer portion forms a recess that contains the floating gate, which in turn contains the charge storage function, all within the boundaries of the original capacitor structure footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables both caching and long-term storage in the back end region of semiconductor devices by maintaining data retention without additional complexity or cost, while allowing for series configuration to implement neural networks based on floating gate resistances.
Implementation Method 1
a portion of the dielectric layer is between the gate structure and the word line conductive structure
Data Source
AI summary
A semiconductor device may include a non-volatile memory cell structure that may be formed in a back end region of a semiconductor device. The non-volatile memory cell structure may include a floating gate structure in which a portion of a dielectric layer is included between a gate structure and a word line conductive structure. The separation of the gate structure and the word line conductive structure by the dielectric layer results in the gate structure being a floating gate structure. This enables a charge to be selectively stored on the gate structure, even when power is removed from the word line conductive structure. The non-volatile memory cell structure along with a volatile memory cell structure are provided in the back end region of the semiconductor device, such that caching and long-term storage may be performed in the back end region of the semiconductor device.