Back-etched Conductive Structures for Reduced Parasitic Capacitance
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Solution Overview
Problem
The formation of strain material overgrowth regions adjacent transistor gates in integrated circuits leads to high parasitic fringing capacitances, which reduce operational speed and performance due to the narrow lateral gap between the overgrowth regions and the gate sidewall.
Innovation Solution
A method is introduced to fabricate integrated circuits where the raised electrically-conductive structures, such as strain material overgrowth regions, are back-etched to increase the width of the lateral gap, thereby reducing parasitic fringing capacitance between the structures and the gate stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If strain material overgrowth regions are formed adjacent transistor gates to provide stress and enhance performance, then transistor drive current and switching speed are improved, but parasitic fringing capacitances increase due to narrow lateral gaps
Solution Approach 1:
The patent removes portions of the strain material overgrowth regions through selective etching processes. This extraction reduces the volume of conductive material adjacent to the gate, thereby decreasing parasitic fringing capacitance while preserving the essential stress-inducing function of the remaining strain material in the source/drain regions.
Solution Approach 2:
The patent applies different treatments to different regions of the strain material. The strain material is preserved in the source/drain regions to maintain stress engineering benefits, while selective portions adjacent to the gate are removed to reduce capacitance. This local differentiation optimizes both performance enhancement and parasitic reduction.
2Strength
If strain material overgrowth regions are formed to increase stress on the channel region, then carrier mobility is enhanced, but the lateral gap between overgrowth regions and gate sidewall decreases
Solution Approach 1:
The patent selectively removes strain material from regions where it creates harmful capacitance effects while preserving it in regions where it provides beneficial stress. This extraction maintains adequate lateral spacing between overgrowth regions and gate sidewalls, preventing excessive capacitance formation.
Solution Approach 2:
The patent modifies the dimensions and distribution of strain material overgrowth regions through controlled etching. By changing the volume and spatial configuration of the strain material, the lateral gap width is increased to reduce parasitic capacitance while maintaining sufficient stress in the channel region to preserve carrier mobility enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances the performance of integrated circuits by reducing parasitic fringing capacitances, leading to improved switching speed and overall operational efficiency.
Implementation Method 1
the raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance
Implementation Method 2
etching cavities in the S/D regions and epitaxially growing a chosen strain material within the cavities
Data Source
AI summary
Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device.