Back-Exposed Masking for CMOS TFT Fabrication
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Solution Overview
Problem
The fabrication of thin film transistors (TFTs) and organic light emitting display devices (OLEDs) requires a large number of masking steps, leading to increased time, cost, and complexity, particularly when implementing CMOS TFTs with LDD regions to reduce leakage current and address hot carrier effects.
Innovation Solution
A method is developed to reduce the number of masking steps by using a back-exposure process to pattern semiconductor layers and ashing techniques, allowing for the simultaneous formation of NMOS and PMOS TFTs on a single substrate with fewer masks, and employing silver or silver alloys with transparent conductive layers to simplify electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple masking steps are used to form NMOS and PMOS TFTs with LDD regions, then the leakage current is reduced and hot carrier effects are addressed, but the fabrication time and process complexity increase significantly
Solution Approach 1:
The patent combines multiple masking steps into a single masking operation by forming both NMOS and PMOS transistor regions simultaneously. The method uses a unified mask pattern that defines both n-type and p-type semiconductor regions in one step, eliminating the need for separate masking processes for each transistor type and each doping region.
Solution Approach 2:
The patent segments the semiconductor layer into different doped regions (n-type and p-type) within a single continuous layer structure. By forming the semiconductor layer once and then selectively doping different portions, the method avoids the need for separate semiconductor layer formations for each transistor type, reducing process steps while maintaining device performance.
2Reliability
If multiple masking steps are used to form NMOS and PMOS TFTs with LDD regions, then the transistor performance is improved, but the manufacturing cost increases
Solution Approach 1:
The patent merges multiple doping operations into a single ion implantation step by using a unified mask that patterns both n-type and p-type regions simultaneously. This reduces the number of mask alignment operations, decreases material consumption, and lowers overall manufacturing costs while maintaining the required transistor performance characteristics.
3Reliability
If multiple masking steps are used for forming semiconductor layers and doping regions, then the device performance is enhanced, but the process complexity increases
Solution Approach 1:
The patent combines the formation of n-type and p-type semiconductor regions into a single masking and doping operation. The mask is designed with patterns that simultaneously define both transistor types, and the ion implantation process deposits both n-type and p-type dopants in one step, significantly reducing process complexity while maintaining device performance.
Solution Approach 2:
The semiconductor layer serves multiple functions: it forms the base structure for both NMOS and PMOS transistors, and it provides the substrate for both n-type and p-type doping regions. This multi-functional approach eliminates the need for separate semiconductor layer formations and doping processes for each transistor type.
4Manufacturing precision
If conventional masking methods are used, then precise pattern formation is achieved, but the number of masking steps increases production time
Solution Approach 1:
The patent merges multiple pattern formation operations into a single masking step. The mask is designed to simultaneously pattern both NMOS and PMOS transistor regions, as well as define the boundaries of LDD regions, in one alignment operation. This maintains the precision required for complex CMOS structures while doubling the production efficiency by eliminating sequential masking steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces production costs, and enhances yield by minimizing the number of masking steps, thereby improving the efficiency and reliability of CMOS TFTs and OLEDs.
Implementation Method 1
forming a first photoresist mask over the semiconductor layer; selectively etching the semiconductor layer using the first photoresist mask
Implementation Method 2
projecting light to the first photoresist mask in a direction such that the light passes through the substrate before reaching the first photoresist mask, wherein the first and second gate electrodes block the light directed thereto
Implementation Method 3
selectively doping the first semiconductor layer using the second photoresist mask. Doping may comprise injecting impurities into the portions of the first second semiconductor layer that are not overlapping the second photoresist mask
Data Source
AI summary
Methods of fabricating a TFT and an OLED using the same are provided. The method of fabricating a CMOS TFT includes: preparing a substrate having first and second TFT regions; forming a gate electrode on the substrate; forming a gate insulating layer on the entire surface of the substrate including the gate electrode; forming a semiconductor layer on a predetermined region of the gate insulating layer using a mask; exposing the back of the mask using the gate electrode; injecting n-type impurity ions into the semiconductor layers of the first and second TFT regions using the back-exposed mask and forming a channel region and source and drain regions; ashing both sides of the back-exposed mask; injecting low concentration impurity ions into the semiconductor layers of the first and second TFT regions using the ashed mask and forming an LDD region; and injecting p-type impurity ions into the semiconductor layer of the second TFT region and forming source and drain regions.