Back-Gate Asymmetrical SRAM Cell for Read Stability
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Solution Overview
Problem
In advanced very large scale integration (VLSI) technology, increased process variation causes significant threshold voltage fluctuation, leading to instability in static random access memory (SRAM) due to large threshold voltage mismatches between neighboring transistors, particularly during the READ mode, resulting in data loss and limited improvement in static noise margin (SNM).
Innovation Solution
The implementation of back-gate controlled asymmetrical SRAM cells with five transistors instead of six, utilizing a dual-gate transistor with independent front and back gates, where the back gate aids inverter functionality and improves read stability, and the front gate handles access, enhancing the SRAM's operating margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional six transistor SRAM is used, then basic memory functionality is achieved, but read stability deteriorates due to threshold voltage mismatches between neighboring transistors
Solution Approach 1:
The patent employs asymmetrical inverter sizing where the first inverter has a larger transistor width-to-length ratio than the second inverter. This asymmetry compensates for threshold voltage mismatches between neighboring transistors by creating intentional design variations that counterbalance process-induced variations, thereby improving read stability without requiring higher manufacturing precision
Solution Approach 2:
The patent applies different transistor sizing strategies to different locations within the memory cell. Specifically, the access transistor connected to the first inverter has optimized dimensions compared to the access transistor connected to the second inverter, allowing each transistor to be locally optimized for its specific function and position, thus mitigating the impact of threshold voltage mismatches
2Reliability
If asymmetrical SRAM cell is used to improve static noise margin, then read stability improves, but device area increases due to additional transistors
Solution Approach 1:
The patent merges the access transistor function with the inverter transistor function by using the same transistor for both purposes. The first access transistor serves dual roles as both an access device and as part of the first inverter, eliminating the need for separate dedicated access transistors and reducing the overall cell area while maintaining asymmetrical noise margin properties
3Productivity
If device size is reduced for advanced VLSI integration, then integration density increases, but process variation increases causing threshold voltage fluctuation
Solution Approach 1:
The patent uses asymmetrical transistor sizing within the memory cell to compensate for process variations that become more significant at smaller device dimensions. By intentionally designing inverters with different transistor width-to-length ratios, the circuit becomes more tolerant to the increased threshold voltage fluctuations inherent in advanced VLSI processes, allowing higher integration density without sacrificing reliability
Data Source
AI summary
Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.