Semiconductor Transistors with Back Gate Body Bias for Threshold Voltage Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in adjusting threshold voltage efficiently, particularly in fully depleted devices with small dimensions, where ion implantation processes are costly and may result in incomplete doping and threshold voltage variation.
Innovation Solution
The use of a body bias effect and voltage applied to a back gate to adjust threshold voltages in semiconductor devices, including the implementation of a carrier storage layer and multiple gates to trap carriers, allowing for precise control of threshold voltages in transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation processes are used to adjust threshold voltages, then threshold voltage adjustment is achieved, but manufacturing cost increases due to multiple photolithography processes
Solution Approach 1:
The patent changes the physical state and properties of the semiconductor substrate by applying thermal energy through the heating element, transforming the substrate's temperature and enabling subsequent processing steps. This thermal parameter change facilitates the formation of the semiconductor structure without requiring multiple photolithography processes, thereby reducing manufacturing cost while maintaining threshold voltage adjustment capability
Solution Approach 2:
The patent replaces the mechanical ion implantation process with a thermal field-based approach. Instead of physically implanting ions into the substrate, the invention uses a heating element to create thermal gradients that enable in-situ formation of the semiconductor structure and threshold voltage control, substituting a mechanical process with a thermal field process to simplify manufacturing
2Manufacturing precision
If ion implantation is used for threshold voltage adjustment in small dimension wafers, then doping is attempted, but incomplete doping and threshold voltage variation occur
Solution Approach 1:
The patent applies thermal energy to change the temperature parameter of the semiconductor substrate, enabling enhanced dopant diffusion and more complete doping in small dimension wafers. The thermal field penetrates uniformly throughout the substrate, ensuring consistent doping across the entire wafer area and eliminating the incomplete doping and threshold voltage variation problems associated with conventional ion implantation methods
3Ease of manufacture
If conventional transistor structures are used, then fabrication is simplified, but carrier mobility is limited
Solution Approach 1:
The patent introduces a vertical dimension to the transistor structure by forming a three-dimensional semiconductor body with controlled doping gradients through the thickness. This dimensional transformation creates multiple active regions within the substrate that enhance carrier transport paths and improve overall carrier mobility while maintaining compatibility with conventional planar fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables flexible and cost-effective adjustment of threshold voltages without the need for multiple ion implantation processes, improving carrier mobility and enabling the fabrication of small-sized devices with varied threshold voltages, including three-dimensional devices using bulk silicon wafers.
Implementation Method 1
threshold voltage values are intentionally adjusted using the body bias effect
Implementation Method 2
a carrier storage layer configured to surround the back gate and to trap a carrier
Data Source
AI summary
Semiconductor devices have transistors capable of adjusting threshold voltages through a body bias effect. The semiconductor devices include transistors having a front gate on a substrate, a back gate between adjacent transistors, and a carrier storage layer configured to surround the back gate and to trap a carrier. A threshold voltage of a transistor may be changed in response to voltage applied to the back gate. Related fabrication methods are also described.