Back-Gate CMOS Fabrication With Dielectric Doping for 2D Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current CMOS fabrication methods face challenges in achieving optimal performance for 2D channel-based transistors, particularly in distinguishing between p-type and n-type MOS devices and reducing contact tunneling barriers.
Innovation Solution
The method involves forming CMOS devices with p-type and n-type MOS transistors using two-dimensional channel materials like carbon nanotubes, appropriate channel doping, and selecting specific metals for source/drain contacts to minimize tunneling barriers, along with the deposition and oxidation of dielectric layers to tune threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS fabrication methods are used for 2D channel-based transistors, then manufacturing simplicity is maintained, but device performance and threshold voltage control are insufficient
Solution Approach 1:
The patent applies different dielectric materials to different transistor types: aluminum oxide for n-type MOS transistors and hafnium oxide for p-type MOS transistors. This local differentiation enables precise threshold voltage control for each transistor type, improving device performance while maintaining a systematic fabrication approach
Solution Approach 2:
The patent changes the dielectric material parameter based on transistor type. By selecting specific dielectric materials (aluminum oxide for NMOS, hafnium oxide for PMOS) with different electrical properties, the threshold voltage can be precisely tuned for each device type, resolving the performance limitation of conventional methods
2Reliability
If appropriate channel doping and metal selection are implemented, then contact tunneling barriers are reduced and NMOS behavior is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent selects specific metal materials for source/drain contacts based on transistor type: aluminum for n-type MOS and tungsten for p-type MOS. This localized material optimization reduces contact tunneling barriers for each transistor type, improving reliability while maintaining manufacturability through standard semiconductor processing
Solution Approach 2:
The patent changes the contact material parameter to optimize electrical properties. By matching metal work function with the respective transistor type, contact tunneling barriers are minimized, enabling proper NMOS behavior and improved device performance
3Manufacturing precision
If dielectric doping layers are deposited and oxidized to tune threshold voltages, then transistor threshold voltage control is improved, but fabrication process steps increase
Solution Approach 1:
The patent performs dielectric layer deposition and oxidation as preliminary steps before transistor fabrication. By preparing the dielectric layers (aluminum oxide for NMOS, hafnium oxide for PMOS) in advance, threshold voltage control is enabled while integrating smoothly into the overall fabrication flow
Solution Approach 2:
The patent applies different dielectric doping and oxidation treatments to different transistor regions. Aluminum oxide layers are processed for n-type transistors while hafnium oxide layers are processed for p-type transistors, enabling precise local threshold voltage control without requiring complete process rework
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables proper NMOS behavior by increasing threshold voltage and reducing contact tunneling barriers, ensuring effective performance of CMOS devices.
Implementation Method 1
depositing a dielectric doping layer comprising aluminum oxide or hafnium oxide over and contacting the first low-dimensional semiconductor layer
Implementation Method 2
tune threshold voltages
Implementation Method 3
the depositing the dielectric doping layer comprises depositing an aluminum layer; oxidizing the aluminum layer to form a first aluminum oxide layer
Data Source
AI summary
A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.