Back-Gate CMOS With Dielectric Doping for Correct NMOS Behavior
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current CMOS fabrication methods face challenges in achieving proper NMOS behavior and reducing contact tunneling barriers in 2D semiconductor devices, particularly with carbon nanotube channels, where NMOS devices often exhibit PMOS behavior and high tunneling barriers.
Innovation Solution
The method involves forming CMOS devices with p-type and n-type MOS transistors using carbon nanotube channels, appropriate channel doping, and selecting specific metals for source/drain contacts to reduce tunneling barriers, along with forming dielectric doping and passivation layers using aluminum or hafnium oxides to tune threshold voltages and ensure proper NMOS behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS fabrication methods are used for 2D semiconductor devices, then manufacturing simplicity is maintained, but NMOS devices exhibit incorrect behavior (PMOS behavior) and high contact tunneling barriers
Solution Approach 1:
The patent applies local quality by implementing different doping strategies for NMOS and PMOS devices. Specifically, aluminum oxide is deposited only on the channel region of NMOS devices to induce n-type behavior, while PMOS devices receive no such doping. This localized treatment ensures each transistor type exhibits its intended electrical characteristics without affecting the other, resolving the issue of NMOS devices exhibiting PMOS behavior.
Solution Approach 2:
The patent changes the threshold voltage parameter of NMOS devices by depositing aluminum oxide on the channel region. This dielectric layer modifies the electrical parameters of the NMOS device, shifting the threshold voltage to achieve proper n-type MOS behavior. The same parameter change is not applied to PMOS devices, maintaining their p-type characteristics.
2Reliability
If conventional contact metals are used, then manufacturing simplicity is maintained, but high contact tunneling barriers are present
Solution Approach 1:
The patent applies local quality by selecting specific contact metals for NMOS and PMOS devices based on their respective channel materials. For NMOS devices with certain 2D channels, metals with lower work functions are chosen to reduce tunneling barriers, while PMOS devices use different metal selections. This localized metal optimization reduces contact tunneling barriers without requiring a completely new fabrication process.
3Reliability
If no channel doping is applied, then manufacturing simplicity is maintained, but proper NMOS behavior cannot be achieved
Solution Approach 1:
The patent introduces aluminum oxide as an intermediary material deposited on the channel region of NMOS devices. This dielectric layer acts as a mediator to induce n-type behavior and control threshold voltage without requiring direct chemical doping of the 2D channel material. The intermediary approach simplifies the doping process while achieving the desired electrical characteristics.
Solution Approach 2:
The patent replaces conventional chemical doping methods with physical deposition of aluminum oxide. Instead of introducing dopant atoms through chemical processes, the threshold voltage control is achieved by depositing a dielectric layer that modifies the electrical field at the interface. This substitution simplifies the manufacturing process while achieving reliable NMOS behavior.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances NMOS device performance by increasing threshold voltage and reducing contact tunneling barriers, ensuring correct operation when a positive Vgs is applied, while maintaining PMOS device performance unchanged.
Implementation Method 1
depositing a dielectric doping layer comprising aluminum oxide or hafnium oxide over and contacting the first low-dimensional semiconductor layer
Data Source
AI summary
A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.