Back-Gate CMOS With CNT Channels for NMOS Threshold Tuning
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Solution Overview
Problem
Existing CMOS fabrication methods face challenges in achieving optimal performance of both PMOS and NMOS devices due to issues with channel doping and contact tunneling barriers, particularly in two-dimensional semiconductor electronic devices.
Innovation Solution
The method involves forming CMOS devices with carbon nanotube channels, using different metals for source/drain contacts to reduce tunneling barriers, and applying dielectric doping layers like aluminum oxide or hafnium oxide to tune the threshold voltage of NMOS devices, ensuring proper NMOS behavior and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS fabrication methods are used, then manufacturing process is simple, but NMOS device performance is poor due to insufficient threshold voltage and high contact resistance
Solution Approach 1:
The patent applies local quality by using different metals for PMOS and NMOS source/drain contacts. Specifically, tungsten is used for PMOS contacts while copper or aluminum is used for NMOS contacts, allowing each device type to have optimized contact properties tailored to its specific electrical requirements, thereby improving overall device performance without uniformly complicating the entire fabrication process
Solution Approach 2:
The patent implements preliminary action by forming a doping layer in the semiconductor substrate before forming the transistor structures. This pre-doping step prepares the substrate with appropriate carrier concentrations in advance, enabling better control of threshold voltage and reducing contact resistance during subsequent processing steps, thus improving NMOS performance proactively rather than reactively
2Reliability
If same metal is used for both PMOS and NMOS contacts, then manufacturing process is simple, but contact tunneling barriers are high reducing conductivity
Solution Approach 1:
The patent applies local quality by using different metals for PMOS and NMOS source/drain contacts. Specifically, tungsten is used for PMOS contacts while copper or aluminum is used for NMOS contacts, allowing each device type to have optimized contact properties tailored to its specific electrical requirements, thereby improving overall device performance without uniformly complicating the entire fabrication process
Solution Approach 2:
The patent implements parameter changes by varying the metal material parameter for contacts based on device type. By selecting different metals with appropriate work functions and electrical properties for PMOS versus NMOS contacts, the patent optimizes contact tunneling barriers and conductivity for each device type, achieving superior electrical performance through material parameter optimization
3Reliability
If no dielectric doping layer is applied, then fabrication process is simple, but threshold voltage control is insufficient for proper NMOS behavior
Solution Approach 1:
The patent implements preliminary action by forming a doping layer in the semiconductor substrate before forming the transistor structures. This pre-doping step prepares the substrate with appropriate carrier concentrations in advance, enabling better control of threshold voltage and reducing contact resistance during subsequent processing steps, thus improving NMOS performance proactively rather than reactively
Solution Approach 2:
The patent uses a dielectric doping layer as an intermediary between the semiconductor substrate and the transistor structures. This intermediate layer serves as a mediator to control threshold voltage by providing a controlled doping profile that modulates the electrical properties of the underlying substrate, enabling precise threshold voltage adjustment without directly modifying the transistor channel structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of NMOS devices by increasing threshold voltage and reducing contact tunneling barriers, resulting in improved conductivity and functionality of CMOS devices.
Implementation Method 1
depositing a dielectric doping layer comprising aluminum oxide or hafnium oxide over and contacting the first low-dimensional semiconductor layer
Implementation Method 2
forming first source/drain contacts on opposing sides of the first gate electrode, wherein the first source/drain contacts are in contact with first opposing portions of the first low-dimensional semiconductor layer
Data Source
AI summary
A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.