Back-Gate CNFET Architecture for Sub-3 nm Scaling
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Solution Overview
Problem
Current transistor technologies face challenges in scaling beyond sub-3 nm technology nodes due to increased parasitic capacitances and energy delay product (EDP) degradation, necessitating the development of new nanomaterial-based solutions to maintain energy efficiency and reduce manufacturing costs.
Innovation Solution
The development of back-gate carbon nanotube field-effect transistors (CNFETs) with a contacted gate pitch (CGP) of 30 nm or less, featuring a channel with a source and drain on one side and a gate on the opposite side, which reduces parasitic capacitance and allows for scaling to sub-3 nm technology nodes while maintaining energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional top-gate and gate-all-around FET architectures are used, then manufacturing is straightforward, but parasitic capacitances increase and EDP degrades when scaling below sub-3 nm nodes
Solution Approach 1:
The patent inverts the conventional gate positioning by placing the gate at the back (opposite side) of the channel rather than at the front or surrounding it. This back-gate configuration reduces parasitic capacitances between the gate and source/drain regions, thereby improving EDP while maintaining manufacturability through modified existing fabrication processes
2Productivity
If contacted gate pitch (CGP) is reduced to scale transistors to smaller technology nodes, then transistor density increases, but parasitic capacitances increase and EDP benefits are degraded
Solution Approach 1:
The patent positions the gate on the opposite side of the channel from the source and drain contacts, effectively utilizing the vertical/dimensional space rather than lateral spacing. This allows CGP to be reduced for higher density while the gate remains spatially separated from source/drain, minimizing parasitic capacitance coupling
3Area of stationary object
If physical spacing between metal gate and metal source/drain is reduced, then transistor area decreases, but parasitic capacitances increase
Solution Approach 1:
By inverting the gate position to the back side of the channel, the patent enables reduced transistor area through smaller spacing while the gate remains physically separated from source/drain regions, preventing parasitic capacitance increase that would normally accompany reduced spacing
Data Source
AI summary
A back-gate carbon nanotube field effect transistor (CNFETs) provides: (1) reduced parasitic capacitance, which decreases the energy-delay product (EDP) thus improving the energy efficiency of digital systems (e.g., very-large-scale integrated circuits) and (2) scaling of transistors to smaller technology nodes (e.g., sub-3 nm nodes). An exemplary back-gate CNFET includes a channel. A source and a drain are disposed on a first side of the channel. A gate is disposed on a second side of the channel opposite to the first side. In this manner, the contacted gate pitch (CGP) of the back-gate CNFET may be scaled down without scaling the physical gate length (LG) or contact length (LC). The gate may also overlap with the source and/or the drain in this architecture. In one example, an exemplary CNFET was demonstrated to have a CGP less than 30 nm and 1.6× improvement to EDP compared to top-gate CNFETs.