Back-Gate Common-Mode Feedback for High-Gain Differential Amplifiers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional common-mode feedback circuits for fully differential amplifiers require a large number of transistors, leading to high power consumption and increased silicon area, with transistors in the triode region resulting in low intrinsic gain.
Innovation Solution
A common-mode feedback circuit using three transistors with back-gate terminals, specifically FDSOI transistors, to provide feedback, reducing the number of transistors required and utilizing back-biasing to achieve high loop gain and efficient power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional common-mode feedback circuits use multiple transistors arranged in current mirror configuration with triode region biasing, then the circuit can provide common-mode feedback functionality, but the number of transistors increases to at least five, resulting in increased power consumption and larger silicon area
Solution Approach 1:
The patent merges the common-mode feedback functionality into a reduced transistor configuration by eliminating the separate current mirror transistors. The common-mode feedback is achieved using only three transistors (M1, M2, M3) where the feedback mechanism is integrated directly into the amplifier structure, combining multiple functions into a compact design that reduces the total transistor count from five or more to just three transistors.
Solution Approach 2:
The patent changes the operating region parameter of the transistors from triode region to saturation region. This parameter change enables the transistors to operate with higher intrinsic gain while maintaining common-mode feedback functionality. The saturation region operation allows the three transistors to provide both the feedback action and the necessary signal amplification that previously required additional transistors in the triode configuration.
2Ease of operation
If transistors are biased in triode region to simplify circuit operation, then the circuit is easier to operate, but the intrinsic gain of the devices becomes very low
Solution Approach 1:
The patent changes the operating region parameter from triode to saturation, which fundamentally alters the transistor characteristics. In saturation region, transistors exhibit high intrinsic gain due to the square-law relationship between gate voltage and drain current, while still maintaining relatively simple circuit operation. The biasing scheme ensures transistors operate in saturation with appropriate Vgs and Vds voltages, achieving both high gain and operational simplicity.
3Reliability
If more transistors are used in the common-mode feedback circuit, then the common-mode feedback loop can be more robust, but the silicon area required increases significantly
Solution Approach 1:
The patent merges the feedback loop functionality into a compact three-transistor configuration that achieves robust common-mode feedback without requiring additional transistors. The feedback robustness is maintained through proper biasing and the inherent gain of saturation-region transistors, eliminating the need for separate feedback transistors that would increase silicon area.
Solution Approach 2:
Each transistor in the three-transistor configuration performs multiple functions: M1 and M2 provide both differential amplification and common-mode feedback action, while M3 provides the tail current and additional feedback control. This multi-functionality allows the circuit to achieve robust feedback performance with minimal transistor count, reducing silicon area while maintaining feedback loop reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves power savings and reduces silicon area while maintaining high loop gain for a wide range of common-mode voltages, improving common-mode rejection for large signals and reducing noise in radio communication devices.
Implementation Method 1
the back-gate terminal of the first transistor is arranged to receive a common-mode reference voltage input
Implementation Method 2
the back-gate terminal of the second transistor is arranged to receive a positive output voltage from the fully differential amplifier
Implementation Method 3
the back-gate terminal of the third transistor is arranged to receive a negative output voltage from the fully differential amplifier
Implementation Method 4
specifically FDSOI transistors, to provide feedback, reducing the number of transistors required and utilizing back-biasing to achieve high loop gain
Data Source
AI summary
A common-mode feedback circuit for a fully differential amplifier comprises first (MB), second (MTP), and third (MTN) transistors, each having a respective drain, source, gate, and back-gate terminals. The drain terminal of the first transistor (MB) and the gate terminals of the first, second, and third transistors (MB, MTP, MTN) are connected together at a bias current terminal. The drain terminals of the second and third transistors are connected together at a tail current terminal. The source terminals of the first, second, and third transistors are connected together. The back-gate terminal of the first transistor (MB) is arranged to receive a common-mode reference voltage input (VCM), the back-gate terminal of the second transistor (MTP) is arranged to receive a positive output voltage (VP) from the fully differential amplifier, and the back-gate terminal of the third transistor (MTN) is arranged to receive a negative output voltage (VN) from the fully differential amplifier.